Insulated Metal Substrates Reduce Thermal Impedance

Sep 1, 2001 12:00 PM
By Dave Sommervold, The Bergquist Company, Chanhassen, Minn.

Today's higher reliability electronic systems mandate a need for optimal thermal management solutions. Watt-density goals have generated additional requirements for circuit board platforms that provide very efficient heat transfer. Pushing the power envelope even higher significantly increases the need to maintain acceptable device junction temperatures, and minimize I²R losses in circuit traces. The use of thicker copper foils alone cannot handle the needed heat transfer. The p. c. board's dielectric/electrical isolation material must have low thermal impedance so that it doesn't appreciably restrict the heat transfer from the power devices, magnetic components, or the I²R heat buildup from high currents. Larger selections for the metal base, a full range of foil thickness and the choice of dielectric and thicknesses maximize thermal performance and electrical isolation.

New Thermal Clad LTI employs higher temperature dielectrics to provide optimum material selection and the lowest thermal impedance (0.5°C/W) of materials available based on glass-epoxy or standard IMS. This improved thermal performance yields high current handling capability, lower junction temperatures, and improved thermal transient response. With the 30% reduction in thermal impedance, power devices on existing IMS platforms can realize at least a 10°C reduction in junction temperatures. As a rule of thumb, every 10°C reduction in temperature boosts the MTBF by one-half.

Typical power devices have a linear derating factor of 1.5W/°C, so a 10°C reduction in junction temperature relates to as much as a 15W increase in available power.

Companies achieved 100W/in.² and improved reliability. The reduced device junction temperatures virtually eliminated warranty costs related to overheated devices. Incorporating low impedance IMS can improve dc-dc converter performance with higher power and improved reliability in existing package sizes. Additionally, no changes are necessary for the module manufacturing process.

The new low thermal impedance IMS challenges companion technologies based on ceramic substrates. In one particular application, using a low thermal impedance IMS produced a measurable decrease in device junction temperature over the existing thick-film substrate. Combined with greater thermal-mechanical durability, low thermal impedance IMS improved overall performance compared with direct bond copper (DBC) in specific applications.

By improving thermal performance, reducing die size, or changing to a lower cost, higher R_DS(on) power MOSFETs can be feasible. Using representative devices utilized in low thermal impedance IMS applications, cost reductions are possible: a 78% increase in R_DS(on) yields a 31% reduction in component cost and reductions of 13% to 57% can be realized for reduced die size.

Improved performance for thermal impedance and thermal transient response minimizes the costs associated with temperature matching power devices. In applications where total harmonic distortion (THD) is important, maintaining equilibrium between device junction temperatures is critical. The thermal performance of the mounting platform helps control the temperature difference between devices. A secondary benefit of not having to temperature match components is that during test and burn-in; if one device fails, both devices don't have to be changed.

Reductions of copper foil thickness are possible because of the improved thermal performance. Typically, you need thicker copper for heat spreading or to deal with I²R heat buildup in the high current traces. By changing to a lower copper thickness, cost reduction in the finished IMS-based circuit board could range 3% or more.

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