MOSFET is Thermally Enhanced for DC-DC

Nov 1, 2004 12:00 PM
By Yalcin Bulut, Account Manager, Market Development — Communications, Vishay Siliconix, Santa

The SO-8 has been the most popular package type used for power MOSFETs in dc-dc converters for more than a decade. The package is well understood and allows for the delivery of a useful MOSFET with acceptable performance. The SO-8 has been used in this application because a combination of moderate on-resistance and low gate charge has been seen as the optimal combination for an efficient design.

Historically, the thermal conductivity of the SO-8 package offered an acceptable level of power dissipation. The resulting temperature rise was relatively low and could be accommodated within the design limits of the PCB conductive cooling system found on most power converters. However, the SO-8 package is not enough for today's demanding design requirements due to its poor thermal characteristics. The package can only dissipate most of the heat through the PCB and is not easy to heatsink.

The criterion for determining the optimum thermal package for the MOSFET is its ability to conduct heat away from the silicon, limiting the temperature rise on the surface of the die to less than 150°C without occupying excessive board space. Steady-state thermal resistance, R_qJC, is the thermal resistance between a semiconductor device's junction and a specified reference point on the device's case or package. R_qJC values represent a baseline upon which drain current, I_D, and device power dissipation, P_D, values are derived. The lower the R_qJC values, the higher the I_D and P_D values, respectively, which means a much more efficient design.

Today's dc-dc converters can generate large amounts of power despite their small size. As power converters become smaller, maximum MOSFET space utilization is critical. This need is addressed by a new surface-mount package technology called PolarPAK, which offers double-sided cooling in an encapsulated body occupying an SO-8 footprint. The new package construction helps reduce R_qJC to about 3°C/W on the top of the package and 0.8°C/W at the bottom of the package. The topside cooling helps divert the dissipated heat directly into a heatsink away from the circuit board, significantly improving the current-handling capability of the package. The silicon is placed on a common lead-frame eliminating the need for a different layout every time the die size changes.

In applications where a large die area is required, an increasingly popular approach is to assign the required silicon area to several power MOSFETS working in parallel. The new PolarPAK package is easy to parallel and aids the board designer in positioning power components close to the powertrain while preventing excessive heat buildup in that area of the PCB (Fig. 1).

Thermal Performance

The power loss in a dc-dc converter is a combination of conduction losses and switching losses. Maximizing the transfer of energy away from the MOSFET die will improve efficiency, because r_DS(on) is proportional to temperature. The relationship between die temperature and conduction loss can be described by the following equation:

Ts = C/(1-C/125)

Where:

C = R_qJA × I² × r_DS(on) (25°C) × K

K = Normalized variation of r_DS(on) with temperature (typically around 1.8).

A power MOSFET generates internal heat due to the current passing through the channel. This self-heating raises the junction temperature of the device above that of the PCB to which it is mounted, causing significant increase in heat dissipation. Maximum efficiency in dc-dc converters can be achieved by selecting the appropriate package to carry out the switching application, reducing heat buildup in the die area by means of good thermal conductivity within the MOSFET, and effectively using board space with packages that can accommodate a large silicon area. Minimizing the increase in junction temperature will help minimize the increase in die (silicon) temperature in a power MOSFET package; hence, this increases the overall system efficiency.

The thermal simulation models shown use 2.5 W of power dissipated by a 13-mm² die and a 1-in. × 1-in. FR-4 double-sided 0.062-in. thick PCB with 100% copper on both sides. We use such a PCB for datasheet characterizations while specifying the R_q values. The temperature values in the pictures indicate the junction temperature for 2.5 W of power dissipation at an ambient temperature of 25°C. Thermal solutions such as airflow, a heatsink with no airflow, and both heatsink and airflow were considered for these thermal simulations.

As seen in the following experiments, 2.5 W of dissipation in an SO-IC or in the PolarPAK package can produce junction temperatures well in excess of the 150°C and 175°C limits normally specified as maximum allowable values for Tj. However, this high power level demonstrates the capabilities of the SOIC-8 and PolarPAK in dissipating higher levels of power under varying conditions. And as will be shown, once heatsinking is applied to the PowerPAK — which is not an option with the standard SOIC-8 — it becomes possible to dissipate such a high power level and still achieve an acceptable junction temperature.

Fig. 2 compares the standard SOIC-8 package and PolarPAK package at still air (no air flow) and without any heatsink at the above-mentioned conditions. Under these conditions, the junction temperature Tj of the SOIC-8 device is 448°C, whereas that of PolarPAK is about 286°C. In other words, for the same footprint size, the PolarPAK package provides a 162°C reduction in junction temperature when used instead of an SOIC-8 package.

As mentioned before, system performance can be improved when airflow and heatsink are used. Fig. 3 shows the conditions where various amounts of airflow — (a) 100 LFM, (b) 200 LFM and (c) 400 LFM — are used without any heatsink to optimize the power dissipation through the PCB as well as the topside of the package. At an applied power of 2.5 W, the junction temperature for PolarPAK package is 255°C using 100 LFM, and 225°C using 200 LFM.

The junction temperature drops further to 207°C when 400-LFM airflow is used. All of these conditions provide significant performance advantage compared to the Tj of an SOIC-8 package. For example, under same load conditions, the junction temperature of an SOIC-8 package with similar die size would be 448°C (using 100-LFM airflow), 367°C (using 200-LFM airflow) and 315°C (using 400-LFM airflow).

With the use of heatsink and airflow, the PolarPAK package can perform even better by dissipating more heat out of the topside of the package (Fig. 4). Using 400-LFM airflow and 0.5-in.-tall, 3-fin heatsink, the junction temperature for PolarPAK is reduced to 97°C. This reduction in Tj well below the 150°C mark reveals that even greater power dissipation may be possible when heatsinking and forced-air cooling are employed.

Acknowledgment

The author would like to thank Kandarp Pandya for his help on running the thermal simulation images for this article.

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