Optimizing Accuracy of Hysteretic Control

Feb 1, 2006 12:00 PM
By Chunping Song, IC Design Engineer, National Semiconductor, Santa Clara, Calif.

In voltage-mode, hysteretic-controlled dc-dc converters, output capacitor-induced ripple and loop delay are the key sources of error in output voltage regulation.

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Hysteretic control, also known as bang-bang control or ripple regulator control, maintains the converter output voltage within the hysteresis band centered about the reference voltage. The hysteretic-controlled regulator is popular because of its inexpensive, simple and easy-to-use architecture. The greatest benefits of hysteretic control are that it offers fast load transient response and eliminates the need for feedback-loop compensation. The other well-known characteristic is the varying operating frequency.^[1-4]

However, the regulation inaccuracy issue of the hysteretic-controlled converter is almost unknown to engineers. Until now, research on hysteretic regulators has mainly focused on transient analysis and transient modeling.^[1-3] The first analysis of accuracy was performed on a current-mode hysteretic regulator specifically designed to power microprocessors.^[5] However, the regulation accuracy of the more widely used voltage-mode hysteretic-controlled regulators is still unknown.

By analyzing operation of the voltage-mode hysteretic-controlled regulator, the root cause of its inaccuracy can be identified. This analysis also reveals how operating conditions (input voltage [V_IN]; output voltage [V_OUT]; and loop delay [t_D]), component sizes (inductor L, output capacitor C) and parasitic parameters (ESR, ESL, R_DS(ON), DCR, etc.) affect the accuracy of dc regulation. Most importantly, this analysis influences the design process for hysteretic-controlled dc-dc converters and enables practical design tradeoffs to be made.

Sources of Inaccuracy

Fig. 1 shows a simplified hysteretic-controlled voltage regulator and its ideal operating waveforms with only ESR-caused output voltage ripple considered. If output voltage V_O(t) is at or below the level of the reference V_REF minus the hysteresis V_HYS, output of the hysteretic comparator is high and then Q2 is turned off and Q1 is turned on. This is the power stage on-state and it causes the output voltage to increase.

When the output voltage V_O(t) reaches or exceeds the reference V_REF plus the hysteresis V_HYS, the output of the hysteretic comparator turns low and then Q1 is turned off and Q2 is turned on. This is the power stage off-state, and it causes the output voltage to decrease. This hysteretic method of control keeps output voltage within the hysteresis band around the reference voltage, which leads the dc value of output voltage to be the reference voltage, namely V_O=V_REF, without any dc offset.

This conclusion is based on the assumptions that there is only ESR-caused output voltage ripple and that all components used are ideal. However, in practical applications, these assumptions are wrong. Output voltage ripple also includes output capacitor C_O-caused ripple and ESL-caused ripple. And all components used are not ideal, so there will be delay in the whole control loop. Given these realities, can the dc regulation accuracy of a typical hysteretic-controlled regulator used in real applications be guaranteed?

Effects of ESL-Caused and C_O-Caused Ripple

It is well known that output voltage ripple has three elements. The three elements of the output capacitor that contribute to output voltage ripple are ESR, ESL and capacitor C_O. Assume that all three elements are in series and there are no other parasitic components to consider. Fig. 2 shows the voltage waveforms across each component of the output capacitor. These waveforms are described by the following equations. These equations define the ESR voltage components differently depending on whether the high-side MOSFET Q1 is turned on or the low-side MOSFET Q2 is turned on.

The voltage waveform across ESR with Q1 turned on is:

With Q2 turned on, that value becomes:

Similarly, the voltage waveform across the ESL when Q1 is on is:

which, when Q2 is on, becomes:

The last component of the ripple voltage waveform is the voltage waveform across an ideal capacitor with an initial value at the beginning of high-side Q1 on-time of:

which, at the beginning of low-side Q2 turn on, becomes:

From those components, the output voltage ripple waveform can be described as:

The ripple component from ESL causes the voltage steps; ESR causes the ramps; and capacitance causes the curvature in the ripple voltage during the switching transitions.^[4]

First, let's consider the effect of ESL-caused ripple on the dc accuracy. Assume that ESL-caused voltage step is smaller than V_HYS and Fig. 3 shows the output voltage waveform with only ESR- and ESL-caused ripple considered. From this figure, we can see that the output voltage's peak ripple above V_REF is equal to V_HYS, and the output voltage's valley ripple below V_REF is equal to V_HYS, too. Then the dc value of output voltage is still regulated at V_REF without any offset. So ESL-caused ripple has no effect on the dc regulation accuracy as long as it is smaller than the hysteresis band.

Next, let's consider the output capacitor C_O-caused ripple's effect on the dc accuracy. There are two cases that need to be considered. The first case is that C_O is big and so C_O-caused output ripple is small compared with ESR-caused ripple. The output voltage waveform in this case is shown in Fig. 4. Here we can see that output ripple is not a ramp anymore and it has second-order curvature caused by CO-caused ripple. But the output voltage's peak and valley value is still decided by ESR-caused ripple.

In this case, the output voltage's peak ripple above V_REF is equal to V_HYS, and the output voltage's valley ripple below V_REF is equal to V_HYS, too. So, the dc value of the output voltage is still regulated at V^REF without any offset. That means C_O-caused ripple has no effect on the dc regulation accuracy as long as it does not change the ESR-caused peak value of output ripple voltage.

In the second case, where C_O is not very big, C_O-caused output ripple cannot be ignored when compared with ESR-caused output ripple. The output voltage waveform in this case is shown in Fig. 5. From this figure, we can see the curvature of ripple is obvious and the output voltage's peak ripple does not happen at the end of on-time anymore. Now the output voltage's peak ripple happens at the same time during off-time, and it is decided by both C_O-caused and ESR-caused ripple. In this case, the output voltage's peak ripple above V_REF is higher than V_HYS, and the output voltage's valley ripple below V_REF is still equal to V_HYS. Therefore, the dc value of output voltage is not regulated at V_REF anymore. The offset between the dc value of output voltage and its target is equal to half of the output ripple voltage's overshoot over the upper hysteresis band V_HYS, namely V_OS=0.5(V_{PEAK_OFF} - V_HYS).

From this derivation, it can be seen that, for the hysteretic-controlled regulator, C_O may influence the dc regulation accuracy depending on C_O's value. In the following analysis, the range of C_O's value for the second case and the output voltage dc offset in this case are provided.

From the ripple equations given for Fig. 2, the ripple of output voltage during off-time when only ESR- and C_O-caused ripple are considered is:

where ΔI is the ripple current through the output capacitor C_O and D is the duty cycle.

So, the peak value of V_{O_OFF} happens at t_{OFF_MAX} when:

From Eq. 2, we get:

Inserting Eq. 3 into Eq. 1, we can get the peak value of output voltage ripple during off-time:

Therefore, the case where the output ripple voltage's peak value occurs during the off-time happens when V_{PEAK_OFF} is higher than the upper hysteresis band V_HYS(V_HYSເ0.5×ESR×ΔI). Then from Eqs. 3, 4 and 0 ≤t ≤ (1-D)T_S, we can derive the boundary of C_O when V_{PEAK_OFF} is higher than V_HYS:

The dc offset of output voltage under this condition is:

The Effect of Delay

In a hysteretic-controlled regulator, one important nonideal factor is the loop delay. Fig. 6 shows the output voltage waveform with only delay and ESR-caused ripple considered. From this figure, we can see that the output voltage's peak ripple above V_REF is greater than V_HYS, and the magnitude of the output voltage's valley ripple below V_REF is also greater than V_HYS. From Fig. 6, we can see that V_OV, the overshoot over upper hysteresis band V_HYs, and V_UV, the undershoot over lower hysteresis band V_HYS, are:

Then the dc value of output voltage, V_{OS_DELAY}, is:

If we assume the rising delay time and the falling delay time are the same, namely t_DR=t_DF=t_D, then:

From Eq. 9, we can see that the only time there is no dc offset is when V_IN=2×V_O, namely when the duty cycle is 50%. Under any other operating conditions, there will always be dc regulation offset caused by loop delay. And this offset is higher for lower inductance L, higher ESR, delay and the difference between V_IN and V_O.

Design Flow

From the previous analysis, we can see that hysteretic-controlled regulators may have inaccuracy issues in real applications. This inaccuracy is caused mainly by output voltage ripple elements other than ESR-caused ripple and by loop delay. In this section, a design example is presented to demonstrate a design flow for hysteretic voltage regulators that accounts for sources of dc error.

In this example, the hysteretic voltage regulator shown in Fig. 1a is used. And because the LM3475 hysteretic PFET buck controller is used, Q1 and Q2 in Fig. 1a should be changed to a PFET and a diode, respectively.^[6] The design condition and target is: 5 V < V_IN < 10 V, V_O = V_REF = 0.8 V, V_HYS = 21 mV and load current I_O = 1 A.

The operating frequency (f_SW) and other performance characteristics of a hysteretic-controlled regulator depend on external conditions and components. The best approach is first to determine what operating frequency is desirable in the application. In this example, we assume the accepted operating frequency range is 200 kHz ≤ f_SW ≤ 400 kHz.

From the operating frequency estimation equation given in reference 4 at the end of this article:

It is important that ESL meet the following condition: ESL_D+V_HYS×L/V_IN. If it does not, the switching frequency becomes too high and uncontrollable. If C_O is big enough and ESL is small enough, Eq. 10 can be simplified to be:

The peak-to-peak voltage ripple estimation is:

Assume in this example that the peak-to-peak voltage ripple estimation is smaller than V_{RIPPLE_SPEC}=40 mV. Then we have:

Eqs. 10 and 11 show that the switching frequency and the output ripple strongly depend on L, ESR and ESL.

The minimum inductance can be calculated using the following equation:

where ΔI is the allowable inductor ripple current and V_D is the forward voltage drop of the diode. The maximum allowable inductor ripple current should be calculated as a function of output current as shown here:

ΔI_MAX=I_OUT×0.3=0.3 A

Then, by Eq. 12 with f_SW=300 kHz, the inductance L is chosen to be L=10 µH.

Once the inductance value and the desired operating frequency are selected, ESR must be selected based on Eq. 10 or 10a. By using Eq. 10a and t_D≈100 ns for the required operating frequency range, ESR needs to be 70 mΩ ≤ ESR ≤ 170 mΩ. Here we choose ESR=100 mΩ. And this ESR value also needs to satisfy the ripple requirement given in Eq. 11.

Based on the previous analysis of C_O-caused ripple, C_O's affect on the dc regulation accuracy and operating frequency can be eliminated, if for duty cycle D < 0.5:

This equation dictates that C_O≥23 µF for f_SW=200 kHz and C_O≥11 µF for f_SW=400 kHz. Here we can choose C_O=47 µF, C_O=100 µF or C_O=22 µF. Eq. 13 is a conservative estimation of the critical output capacitance because its derivation does not consider the turn-on and turn-off delay. So in real application, C_O can be 22 µF without any affect on dc accuracy.

Once C_O's choice satisfies Eq. 13, the dc regulation inaccuracy is mainly caused by the loop delay. In this case, the dc output voltage offset is:

This offset will be higher when L is lower, ESR is higher, delay is longer, and the difference between V_IN and V_O is greater. If this inaccuracy is not tolerable, the above design steps need to be repeated. Sometimes, it may take several iterations to satisfy all requirements.

As for the selection of other components, such as the input capacitor, diode and MOSFET, it is the same as that in the normal selection process. Bench test results for the component values selected previously are presented in Fig. 7. In Fig. 7, channel 1 is the switch node waveform and channel 3 is the output voltage. From Fig. 7, we can see circuit operation meets the design goal.

References

1. Miftakhutdinov, R. “An Analytical Comparison of Alternative Control Techniques for Powering Next Generation Microprocessors,” TI Seminar, 2002.

2. Yan, Liu, and Sen, P.C. “Large-Signal Modeling of Hysteretic Current-Programmed Converters,” IEEE Trans. on Power Electronics, Vol. 11, No. 3, 1996, pp. 423-430.

3. Tso, C., and Wu, J. “A Ripple Control Buck Regulator with Fixed Output Frequency,” IEEE Power Electronics Letters, Vol. 1, No. 3, 2003, pp. 61-63.

4. “Designing Fast Response Synchronous Buck Regulators Using the TPS5211,” User's Guide, Texas Instruments, June 2000.

5. Song, C., and Nilles, J. “Accuracy Analysis of Hysteretic Current-Mode Voltage Regulator,” Proc. IEEE APEC, 2005, pp. 276-280.

6. “LM3475 Datasheet,” National Semiconductor Corp., January 2005.

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