Phase Shifting Optimizes Multistage Buck Converters

Jan 1, 2007 12:00 PM
By Robert Taylor, Applications Engineer, and Wei Liu, Applications Engineer, Texas Instruments, Dall

Fig. 2 shows the relationship between the normalized input rms current and the duty cycle. The input ripple current cancellation is related to the number of phases and duty cycle. Greater ripple reduction is generally achieved with additional phases. Also, minimum input ripple is found at specific duty cycles related to the number of phases used.

According to the parameters defined by Eq. 1, the input ripple current cancellation factor for the interleaved supply is shown in Eq. 2 and calculated to be 0.084:

Without equal phase shifting, all the high-side MOSFETs could be switched on at the same time. The ac current is sourced by the input capacitors simultaneously and with a very high current slew rate. The rms input ripple current can be calculated for the noninterleaved case as shown in Eq. 3:

This is almost four times the input ripple current of the interleaved approach, which is normalized for various channel counts in Fig. 2. Large ripple current will cause very high power dissipation in the input capacitors due to the capacitor equivalent series resistance (ESR). The capacitor lifetime also will be reduced. The number of capacitors required for the noninterleaved approach will be four times that of the interleaved to maintain the same input voltage ripple.

In addition to the reduction of the input ac rms current, the peak-to-peak current is also reduced due to interleaving. The switching current in the input capacitor is typically a large source of electromagnetic interference (EMI) noise. With the reduced switching current amplitude, the current slew rate is reduced while providing the ac current to the high-side MOSFET. Hence, the EMI noise is reduced. With interleaving, the input ripple frequency will be six times higher than that of single-phase operation. The higher frequency makes the EMI filter smaller and less costly.

Output Ripple Cancellation

Similar to the input ripple cancellation, the output ripple current is also reduced because of interleaving. Reducing the output ripple current allows fewer output capacitors to maintain the same amount of output voltage ripple. Eq. 4 shows the peak-to-peak output ripple current cancellation factor:

where D is the duty cycle for a single phase and NPH is the number of active phases.

The relationship between the peak-to-peak output ripple cancellation factor, duty cycle and phase number is shown in Fig. 3. For a 6-phase 12-V to 1-V converter, the ripple cancellation factor is calculated to be 0.5. Eq. 5 shows the peak-to-peak ripple current for the interleaved case:

Without equal phase shifting, the peak-to-peak output ripple current is considerably higher. Eq. 6 shows the calculation of the peak-to-peak output ripple current for the noninterleaved approach:

This is more than 13 times the peak-to-peak ripple current of the interleaved case. Therefore, a nonphase-shifted approach would require 13 times as much output capacitance to maintain the same output voltage ripple, which adds to the area and cost of the power supply.

Simulation and Experimental Results

The two designs compared input and output ripple voltage and the number of components required to meet the design specifications. In all situations, the interleaved approach was found to have better performance than the noninterleaved approach. The simulation results comparing the two approaches are shown in Table 2.

Parameter	Interleaved	Noninterleaved
RMS input ripple	10.38 A	37.2 A
Peak-to-peak input ripple	24.3 A	145 A
RMS output ripple	0.75 A	10.1 A
Peak-to-peak output ripple	2.65 A	34.7 A
Ripple frequency	1.38 MHz	230 kHz
Table 2. Ripple current simulation results.

Because the ripple current is much higher for the noninterleaved case, many more capacitors are required to meet the specifications. The chosen output capacitors for this application are 4-V, 470-µF, 10-mΩ Specialty Polymer (SP) capacitors from Sanyo. The input capacitors are a mixture of 16-V, 22-µF ceramic capacitors and 16-V, 180-µF OS-CON capacitors. Table 3 shows the voltage ripple results and the required number of capacitors for each case.

Parameter	Interleaved	Noninterleaved
Output voltage ripple	4.8 mV	9.8 mV
470-µF output capacitors	1 per phase	6 per phase
Input voltage ripple	41 mV	99 mV
180-µF OS-CON input capacitors	—	2 per phase
22-µF ceramic input capacitors	1 per phase	4 per phase
Table 3. Ripple voltage and capacitor requirements.

The results show that the interleaved approach provides a significant advantage in terms of number of capacitors for both the input and the output. In addition to the component savings, the input and output voltage ripple is improved.

The experimental results of the interleaved solution were checked to ensure that the simulations are accurate. The measured input voltage ripple is ~60 mV and the output voltage ripple is ~6 mV. Both of these values are close to the simulated results. Fig. 4 shows the input and output voltage ripple of the interleaved supply. In reality, the ripple current cancellation effect will be limited to some extent based on the parasitic component values.