Eliminate the Guesswork in Selecting Crossover Frequency

Aug 1, 2008 12:00 PM
By Christophe Basso, Application Manager, ON Semiconductor, Toulouse, France

Solving for j, we have:

Based on Eq. 10, Eq. 8 can be updated as:

Knowing that the loop gain module at crossover is 1, T(s) can be approximated as:

Based on this result, Eq. 5 can now be updated as:

Solving this equation yields:

As can be seen, the module of the capacitor impedance is now affected by a term dependent on the phase margin. The variations of this term can now be plotted versus the phase margin as proposed by Fig. 6.

As observed, a phase margin below 60 degrees degrades the converter's output impedance, whereas it slightly improves it for a phase margin above 60 degrees.

Design Example

Assuming a power supply with an output capacitor of 1000 µF, the designer needs to make a choice considering the output-voltage ripple conditions and the corresponding rms current circulating in the capacitor. The specification here notes that there should be a maximum voltage drop of 80 mV when the converter undergoes a current step ΔI_OUT of 2 A. What bandwidth is needed to reach this parameter? If Eq. 3 is used and a 2-A step is applied, the voltage drop can be predicted:

From this equation, it is easy to extract the minimum crossover point:

Based on this result, the designer must check that the capacitor ESR is lower than:

A 1000-µF capacitor from the Panasonic FM series could be the right choice. From the manufacturer's data sheet, the capacitor has an ESR of 19 mΩ at 100 kHz. This ESR alone will contribute to a drop of 19 × 10^-3 × 2 = 38 mV, which is 47% of the specification. To offer some margin in this design, increase the crossover frequency to 6 kHz and purposely compensate the converter to meet this goal.

Once compensated, the 5-V voltage-mode buck converter loop-gain Bode plot SPICE simulation appears in Fig. 7. It shows a crossover frequency of 5.8 kHz together with a rather comfortable phase margin of 76 degrees. The output-voltage drop is now going to split between the capacitor and its ESR term. Based on a 76 degree phase margin, the capacitive contribution can be approximated using Eq. 14:

Now step load the output by a current source ranging from 100 mA to 2.1 A in 10 µs (Fig. 9). Fig. 8 shows the simulation results. It can be seen that the total output undershoot is well within the design goals with a theoretical 53.5-mV deviation. The ESR spike is 35 mV and lasts only during the output-current circulation in the capacitor. The capacitive contribution reaches 50 mV, which is a fairly good agreement with the Eq. 14 predictions.

As can be seen, the ESR term amplitude depends on the output-current step. When the load change is slow enough, the loop has a means to attenuate the ESR contribution. However, usually the transient loading conditions are so fast that all the current step translates into a voltage spike over the ESR. Given its steepness, the loop cannot fight it.

The situation degrades further if the output-current rate of change reaches high values, like in motherboard applications for instance. In that case, the inductive term called the capacitor's equivalent series inductance (ESL) starts to enter the picture and the situation worsens. In these extreme cases, the capacitor selection is almost solely based on the contribution of its parasitic terms and no longer on its capacitive value.

Therefore, the designer can analytically select a crossover frequency rather than arbitrarily choosing it based on the switching frequency. If the capacitor impedance plays a role in relationship with the selected crossover frequency, there are other terms whose contribution is out of control, such as the ESR and ESL of the output capacitor. They are respectively sensitive to the output-current step and the current slope. As loop control has almost no influence on their contributions, it is the designer's task to make sure these parasitic terms stay low enough to keep the overall transient response within the original specifications.

References

1. Basso, Christophe, Switch Mode Power Supplies: SPICE Simulations and Practical Designs, McGraw-Hill, 2008.

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