Control Technique Cuts Flyback Input Capacitance

Apr 1, 2007 12:00 PM
By Rahul Joshi, Staff Applications Engineer, Power Integrations, San Jose, Calif.

For flyback power supplies that need long holdup times, a technique called on-time extension maintains regulation with less bulk input capacitance than would be required with conventional, fixed-frequency control.

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Microprocessor-based devices require a regulated power-supply unit (PSU) that detects the loss of input power and continues to supply power for the length of time it takes to complete the process of writing critical data to nonvolatile memory. One approach to designing for continuous power is to generate a higher output voltage and use a linear regulator to produce the lower voltage that is required. The capacitance at the input of the linear regulator is used to provide the holdup time. Unfortunately, this approach degrades the overall power-supply efficiency because it requires a second linear regulator be used, driving the need for a larger transformer and components rated for higher power on the primary side of the power-supply circuit.

Another solution is to use on-time extension, an approach adopted in a series of off-line switching ICs produced by Power Integrations (PI). In the PI chips, on-time extension is combined with an on/off control function to provide voltage regulation. The two techniques replace conventional pulse-width modulation (PWM) control and eliminate the need for additional circuitry (Fig. 1). The TinySwitch-III ICs incorporates a 700-V power MOSFET, an oscillator with frequency jittering for low EMI, a high-voltage switched current source for startup, and a current-limit on/off controller in a single monolithic device.

The power MOSFET connected between S and D in Fig. 1 switches at a frequency and duty cycle defined by the controller and transfers energy from the rectified mains input to the transformer secondary. During normal operation, the switching of the MOSFET is controlled by the EN/UV input. MOSFET switching is disabled when a current greater than 115 µA is drawn from this pin. Hence, a feedback signal from the dc output passing via the optocoupler to the EN/UV input can enable or disable switching of the MOSFET, providing output-voltage regulation that is appropriate to the load conditions. An optional bias winding provides power to the TinySwitch-III device. Without the bias winding, the TinySwitch-III parts can operate in self-powered mode through a high-voltage current source internal to the part.

During normal operation, the maximum duty cycle at which the controller drives the switching element is limited to ensure control-loop and enforce-circuit protection. However, when the input supply is lost and the dc-bus voltage begins to drop, any limiting of the duty cycle will also reduce the amount of energy that can be delivered to the load. To compensate, the on-time extension feature enables a longer holdup time, maximizing the energy delivered from the input capacitor to the output.

Memory-Backup Power Requirements

Applications that require critical data to be stored prior to shutdown frequently use electronically erasable programmable read-only memory (EEPROM) and require a regulated supply voltage be available for the time it takes to complete the memory write cycles. For some EEPROM memories, the write-cycle time may be as long as 10 ms. To provide adequate write-cycle time, a standard practice is to reduce power consumption during the power-down sequence by turning off any peripherals and nonessential loads. Fig. 2 shows the relationship of the dc-bus voltage and the power-down sequence, making effective use of energy stored in the input dc-bus filter capacitance.

The power converter stage needs to use energy stored in the input-filter capacitor to maintain the output voltage within regulation limits. In Fig. 2, this represents the time it takes the dc-bus voltage — after an input failure condition is detected — to drop from V_MIN2 to V _MIN3 and hold for a period of time that is sufficient for data backup.

For most low-power applications, the flyback converter is the topology of choice due to low cost, low component count and ease of design for universal input applications. Two flyback converters will be compared to illustrate the effectiveness of on-time extension and its impact on capacitor selection. One of the flyback converters operates in discontinuous conduction mode, fixed frequency (DCMFF), and the other utilizes on-time extension to implement discontinuous conduction mode, duty-cycle extension (DCMDE).

The operational differences and the resulting benefits are explained using a simple example of a flyback converter operating with 100-kHz operating frequency. A 21.25-W design is used for comparison; it is assumed that both designs use the same transformer and that the value of the primary inductance has been calculated to reach a peak current of 1 A maximum with a 50% duty cycle at the minimum dc-bus voltage of 100 Vdc.

Power Delivery for DCMFF

In this case, the power-delivery capability of a DCMFF conversion stage with a maximum duty cycle of 50% is evaluated for a 21.25-W (5 V at 4.25 A) power-supply design operating at 100 kHz and using a 500-H primary inductance (Fig. 3). Efficiency of 84% is assumed.

The value of V_MIN for this design is 100 Vdc. At a bus voltage of 100 Vdc, the duty cycle will be at its maximum value if the load connected is equal to full-load capacity, which is 21.25 W. The operation of the circuit is as follows:

At time t₀, MOSFET Q1 is turned on. MOSFET Q1 remains on between the interval of t₀ to t₁. During this interval, primary current increases linearly, and its slope is a function of the input dc voltage V_IN. At time t₁, MOSFET Q1 switches off, resulting in a reversal of voltages across the primary and secondary windings of transformer T1. Diode D1 starts conducting at t₁ and diode current decreases linearly until it reaches zero. The peak value of diode D1 current depends on the transformer turns ratio and the value of primary current at t₁. For a discontinuous design, diode current falls to zero before the MOSFET Q1 turns on again at t₂. This operation repeats and energy stored in the primary at the end of the on time of the MOSFET Q1 is transferred to the secondary in every cycle.

With a reduction in input voltage below 100 V, and the duty cycle having reached 50%, which is the maximum for this design, the peak current in the inductor at the end of the on time is lower than the value required for supporting full load at output. The dotted lines in the Fig. 3 waveforms indicate the nature of change expected with a reducing dc-bus voltage, assuming that the load is dropping to maintain a constant output voltage. The slope of the primary inductor current is a function of the input dc voltage. Once the duty cycle reaches 50%, there is no further increase in the duty cycle, and the on time remains fixed for every switching cycle. This results in reduced energy transfer per cycle and a reduction in the maximum power capability of the design, as in Eq. 1:

where P equals power transferred, L equals primary inductance of transformer, I_P equals peak primary current, f equals switching frequency and η equals converter efficiency.

For a DCMFF design with a 50% maximum duty cycle, the relationship between maximum output power and dc-bus voltage is provided by Eq. 2:

Fig. 4 shows that the maximum power capability of the circuit drops with decreasing input voltage; for 50% of a full load, the circuit can maintain regulation at output only down to a dc-bus voltage of 69 Vdc.

Power Delivery for DCMDE

On-time extension without changing the off time automatically results in duty-cycle extension. To enable comparison between the on-time extension method and the DCMFF method, a 50% duty cycle with a V_MIN value of 100 V is assumed. This results in the same value of primary inductance for the circuit to deliver full power at 100-Vdc input, and also results in identical operating conditions for a dc-bus voltage higher than 100 Vdc. The operation of the circuit is identical to the DCMFF configuration until the input dc voltage reduces to a value equal to V_MIN.

As the input voltage drops below V_MIN, the interval from t₀ to t₁ is extended until the primary current reaches the predetermined value of peak primary current, which is equal to the value expected at an input voltage equal to V_MIN and a 50% duty cycle. The interval t₁ to t₂ is kept fixed and is equal to half the time period of the switching frequency under normal operating conditions.

Fig. 5 shows the variation of primary winding current wave shape for reduced input voltages. The inductor current slope reduces as the input voltage reduces; therefore, it takes longer for the primary current to reach the required value of peak current. While this automatically reduces the operating frequency by extending the on-time interval, the energy stored in the inductor for every cycle of operation is essentially constant. A drop in operating frequency results in a reduction of the maximum power capability of the circuit. The curve for the maximum power capability of the circuit as a function of input voltage now follows a different shape (Fig. 4).

The relationship between the minimum input voltage and maximum output power is shown in Eqs. 3 and 4.

where E_L equals energy stored in the primary inductance per cycle, ΔI equals peak-to-peak value of primary current, P_OUT equals output power, η equals converter efficiency, L equals primary inductance and t_OFF equals off time per cycle.

When the two curves are compared, it becomes apparent that the on-time extension scheme can enable the power converter to deliver much higher power at lower input voltages than a DCMFF design would allow. The curves also indicate that, for a 50% load on the output, the DCMFF converter can maintain regulation down to approximately a 69-Vdc bus voltage, whereas the DCMDE converter can maintain regulation to a voltage as low as 31.5 V. Therefore, the DCMDE method enables the power supply to provide a much longer holdup time for memory backup operation and makes better use of the stored energy in the input capacitor.

DC-Bus Filter Capacitance

As indicated in Fig. 6, the dc-bus filter capacitor helps maintain the input voltage seen by the converter stage to a value equal to or higher than V_MIN, which enables the converter to remain in operation and maintain regulation. References 1, 2 and 3 provide detailed methods for calculation of this capacitance value. The energy required by the converter during the interval t_D is supplied by the discharging capacitor. The required capacitance value can be estimated using Eq. 5:

where C equals estimated bulk input capacitance, P_OUT equals converter output power, η equals converter efficiency, t_D equals capacitor discharge interval, V_PK equals minimum peak voltage seen by the power supply at low line and V_MIN equals minimum dc voltage for satisfactory operation.

A value of 90 Vdc or 100 Vdc is an optimum choice for the minimum dc-bus voltage of the converter.^[3] Further reduction in the value of V_MIN can help in reducing the value of the capacitance required at the input. However, this also results in significantly higher peak currents in the primary winding and requires oversizing of the switching elements in the circuit.

If a switching power supply has to remain in operation and provide regulated output voltage during periods of disturbance, its input capacitor must be selected to allow for a minimum input rms voltage of 30% below nominal, approximately 84 Vac for a 120-Vac system.

At any given input supply voltage, time t_D is a function of operating frequency (Fig. 6). Figs. 7 and 8 show the estimated value of input capacitance required for different values of minimum dc-bus voltage (V_MIN) for different converter operating efficiencies. The three sets of curves are for: nominal capacitance without any holdup consideration; a holdup time of 4 ms; and a holdup time of one-half cycle duration of the input supply-line frequency.

For normal operation or operation with short-duration supply-line disturbances, Figs. 7 and 8 provide easy-to-use multiplication factors to determine the required value of capacitance. The value of this capacitance is termed as C_N, or nominal capacitance.

The minimum value of dc-bus voltage to maintain regulation during a power-down sequence can be obtained from Fig. 4 or by using Eqs. 2 and 3. Eq. 8 can then be used to determine the value of capacitance required at the input to ensure sufficient additional holdup time during completion of the power-down sequence:

where C_H equals capacitor required for completing power-down sequence or memory backup, P_R equals reduced output power level during power-down sequence, η_R equals converter efficiency for reduced power level, t_H equals holdup time duration required for power-down sequence, V_S equals dc-bus voltage at the start of the power-down sequence and V_E equals dc-bus voltage up to which regulation can be maintained for reduced power.

If C_H is much greater than C_N, the higher value must be used. It may be possible to increase V_MIN to reduce the difference in the calculated values of C_N and C_H.

For a 20-W, universal-input power supply, which is designed to operate at a dc-bus voltage as low as 100 Vdc and must operate at frequencies as low as 47 Hz, the value of the input capacitor for normal operation or C_N will be approximately 100 µF, assuming the converter is more than 85% efficient (Fig. 7). If the regulated supply must be available for at least 35 ms after input supply failure (to complete the EEPROM write cycle), then sufficient energy must be available in the capacitor C_H.

If the load required during memory backup is 10 W (50% of full load) and the power supply is designed using a fixed-frequency 100-kHz controller with a maximum duty cycle of 50%, the required capacitor value, which can be calculated using Eq. 2, Eq. 5 or Fig. 4, will be 172 µF. If the control scheme of this power supply is modified to use on-time extension, the required value of C_H (which can be calculated using Eq. 5 or Fig. 4) is reduced significantly to 100 µF. Therefore, the input capacitor will not have to be upsized to meet the extended (35-ms) power requirement.

In the preceding example, it is assumed that the converter efficiency drops to 78% when operating at lower dc voltage and at 50% load. (In practical designs, this can be verified on the bench.) This example demonstrates how on-time extension helps to maximize the use of energy stored in the input dc-bus filter capacitor, and thereby increases the hold-time for a regulated power supply.

Limitations of On-Time Extension

Though on-time extension can significantly improve the power delivery of a flyback power supply, care must be taken to ensure that the supply is not required to operate with extended on-time indefinitely. Any increase in on time beyond normal limits will increase rms currents and, therefore, power dissipation in both the MOSFET and the primary windings. Power Integrations' integrated switchers incorporate overtemperature protection. However, continuous operation of the extended on time feature can lead to overheating, reduced efficiency and greater heatsinking requirements, and should therefore be avoided.

Power supplies need correctly sized input capacitors to both ensure satisfactory operation during power-line disturbances and to provide regulated supply for a sufficient amount of time after an input supply failure is detected, to allow for storage of critical data during shutdown in computing devices. The size of the input capacitor for this application can be reduced significantly if an integrated switcher featuring on-time extension is used. In the examples presented, the DCMFF technique (without on-time extension) needs a higher input voltage to deliver the same amount of power as the DCMDE technique (with on-time extension), especially when operating below the design's minimum dc voltage.

References

1. Billings, Keith, Switch Mode Power Supply Design Handbook, Chapter 6, McGraw-Hill Inc., 1989.

2. Chryssis, George C., High Frequency Switching Power Supplies — Theory and Design, McGraw-Hill Inc., 1989, pp. 8-9.

3. TOPSwitch Flyback Design Methodology, Application Note AN-16, Power Integrations, San Jose, California, pp. 13-14.

4. Whitaker, Jerry C., “Power Quality — An Ongoing Challenge — Part 1,” Technical Press, March 24, 1999.

5. IEEE Orange Book (IEEE Recommended Practice for Emergency and Standby Power Systems for Industrial and Commercial Applications), IEEE Standard 446, 1987.

6. Joshi, Rahul, “Input Filter Estimation Method for Flyback Power Supplies with Microprocessor Loads,” Power Electronics Technology Exhibition & Conference 2006.