Automated Fault Diagnosis Ensures Product Success

Apr 1, 2008 12:00 PM
By Tim Ghazaleh, Director of Marketing, Intusoft, Carson, Calif.

Establishing Design Test Limits

Establishing electrical test limits for devices and signal lines is an important aspect of fault simulation, because signals could lead to catastrophic product operation if they falter. The first option for establishing test limits is to probe anywhere in the circuit after a nominal simulation and view signal waveforms. From this the designer might ascertain acceptable deviation for pass/fail test limits. Alternatively, the designer could interpolate such limits from final or maximum values charted after simulation. Other ways of establishing test limits make use of acceptance criteria from product specifications and component data sheet ratings (i.e., device maximum power).

A production-oriented method for establishing test limits is to first run a Monte Carlo statistical analysis, which randomly (i.e., Gaussian variation, bimodal, etc.) varies component parameters through their tolerance range, then examines devices and signal lines for a corresponding change in behavior. Graphical representation of Monte Carlo signal behavior, such as a curve family, enables interpolation of maximum variations within the waveform's envelope caused by the design's altered component tolerances.

The designer also can select a histogram bar graph from the Monte Carlo simulation that shows how many runs fell within a range (bin) of signal values (i.e., seven runs fell within 1.25 mV to 1.3 mV). If necessary, once the design is tweaked enough where signal variations are acceptable, you can use min and max values for this range to establish pass/fail limits on signal lines and devices. Besides understanding how the design will perform with device variation in production, you can use the test limits as pass/fail criteria when injecting faults into the design simulation.

A useful feature is the ability to quickly expand test limits in any number of ways following fault simulation (Fig. 6). Recall earlier that after a fault run, specific test limits were not yet established. Now the “expand to pass” option (left dialog) provides ways to open min/max test limits for all measured readings under the present fault at hand (i.e., Q1 open). Corresponding colored histograms to the right reflect the new pass/fail results. The dialog shows expand-to-pass options:

1. Assignment of any sigma limit (3, 4, 5…), whereby 3 S is taken as a device's assigned tolerance variation (i.e., 5%).

2. Manual value, which the user assigns in the associated “value” box. This could be in compliance with design specifications, the component data sheet, signal waveform data and designer discretion.

3. Expand to pass, which sets the measured value as the high or low limit depending on the sign, or both minimum and maximum limits symmetrically if the “with symmetry” box is checked as in Fig. 6.

Once the designer specifies the test limits, the new limits can be used to study test-limit compliance with successively selected faults — that is, seeing how other faults' measured results comply with the new test limits. For example, Fig. 6 shows test limits expanded for a Q1 open fault, so that all monitored signals and devices pass. But when selecting our former R7 stuck-at fault, three of the pass/fail histograms change color (failed red) despite the new expand-to-pass limits for Q1 open. Fig. 6 shows all devices and signals in a pass condition for Q1 open.

Product Safeguards

So what does all this have to do with design reliability? Beyond reliability analyses such as Monte Carlo and worst case, not much. However, fault simulation does adversely affect a design in several possible ways, which ultimately enables the designer to view measured data that could be critical to production or field operation. Safeguards can then be built into the design to help circumvent hazardous product operation if a fault were actually to occur. For instance, if a signal dropped below a certain voltage resulting from possible component failures found by fault simulation, then special electronics could be built into the design to take a prescribed course of action. Examples include an LED display that a fault condition occurred, invocation of equipment shutdown and activation of backup electronics.

Examine how a design will operate under faulty conditions early in a product's design-simulation phase. Historically, SPICE tools have provided powerful ways of varying component tolerances and temperature to study signal variation for manufacturing compliance. This method and other means also serve to establish pass/fail criteria for acceptable operation under fault conditions. In the end, incorporate product safeguards early in the design cycle to help eliminate possible damage from faults encountered in production and in the field. The process not only saves weeks to months of time using traditional attempts at fault diagnosis, but is far more effective in ensuring accuracy and thorough fault coverage.

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