Automated Fault Diagnosis Ensures Product Success

Apr 1, 2008 12:00 PM
By Tim Ghazaleh, Director of Marketing, Intusoft, Carson, Calif.

A product's future can be at stake if any of its parts fail, such as a short, open or stuck-at condition. To avoid such problems, product designers should be aware of the cause and effect of part failures, as well as their potential risk to the end user. Designers should not have to find this out in the field; they should be able to predict potential failures in the design process. Automated fault diagnosis produces the desired results.

Automated fault diagnosis capability is now available with SPICE-simulation tools for analog and mixed-signal designs. In the past, the lack of this capability forced designers to employ many painstaking tricks by inserting circuit faults one at a time using design-automation tools. Or they might use unconventional circuit board measures with marginal results.

For example, a designer could insert a super-high resistance value (1 GΩ) to simulate an open condition, or insert a wire to simulate a shorted component. Although that is all right for simulation, it is potentially dangerous with a prototype board. Or, the designer could use a heat source to temporarily change a transistor's temperature coefficient on a circuit board. However, inserting faults in a complex IC can create its own set of problems. Manually pursuing fault coverage under any of these conditions could take weeks to set up and attempt measurement, including the need to track an immense amount of design-alteration data.

Automated fault diagnosis spares the designer from such laborious manual tasks. It provides a convenient means of first assigning pass/fail limits to a component's electrical operation and signal levels, such as maximum power, root-mean-square voltage, transistor collector current, rise time and propagation delay. Then the designer assigns shorts, opens and stuck-at values to passive, discrete and active devices. The designer also can assign fault levels for device temperature and power-supply sources. After entering these adverse conditions, the designer can run fault simulations, which automatically simulate all prescribed faults, record designated measurements with pass/fail status and flag out-of-tolerance component conditions.

Fault Simulation Setup

The designer can prepare a fault simulation in either the time or frequency domain. Design simulation setup is done quickly by dialog-box entry, specifying the start/stop points in time for transient analysis, or start/stop frequency and number of points per decade, octave or linear for frequency-domain analysis.

Next, the designer assigns fault conditions. Fig. 1 illustrates this process for a UC1524 PWM controller IC design. The designer can perform this on any device, like R3 in Fig. 1. The type of prescribed fault appears in the “failure mode” dialog for R3 — and optionally all like parts (i.e., resistors). The designer can also do this for power sources, the PWM IC and the device temperature. The “failure parameters” dialog enables the designer to change default values for short and open faults, as well as stuck-at values. After assigning fault conditions in this fashion, only one fault (L1 short) is initially enabled from a failure-mode dialog box, among a large collection of other faults that were previously established.

Next, the designer should select the electrical properties of components and signal lines to monitor during post-fault simulations, including pass/fail status. Fig. 2 includes several signals and devices selected to record their “final value” post-fault simulation. The drop-down list provides several other selectable measurements. The fault run (time domain) was prescribed over a 1-msec period.

Fig. 3 illustrates the resulting measured final-value readings (measurements column) for several signal lines and devices, including their pass/fail status by colored histogram bars. Actual min/max test limits will be described later. For now, default values are automatically assigned by the simulator. In the lower-right corner of the dialog box, L1 short was selected from a drop-down list of several possible faults.

Multiple faults enabled for simulation appear in Fig. 4. Note that four new faults were enabled (Q1 open, R7 stuck at 1 kΩ, R3 short and source V1 stuck at 4.9 V). Fig. 5 shows the simulation results, with display waveforms, pass/fail status and measured results.

Selected for analysis are all five fault selections enabled in Fig. 5, and the R7 stuck-at condition. After simulation, the designer can choose any of the enabled faults atop of the list, which instantly show corresponding changes in the measurement values in the main portion of the dialog box for the prescribed devices and signals.

Next, observe that a detailed breakout of the devices and signals is on the left of the dialog, just under the shaded final-value text. Selecting one of these entities causes the instant display of the corresponding measurement and pass/fail conditions on the right for all five fault conditions. Both ways of displaying measurements and pass/fail status (selecting all devices and signals as a collective group as shown in Fig. 5, or selecting individual ones to display data from all enabled faults) provide a fast what-if analysis of how faults affect critical devices and signal lines. The simulation waveforms show the current through R7 and voltage on signal V(18) atop of the design. Such waveforms also can be displayed in real time during fault runs.

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