Model Current-Mode Control With Ease and Accuracy

Nov 1, 2008 12:00 PM
By Rendon Holloway, Principal Engineer, Fairchild Semiconductor, San Jose, Calif., and Gabriel Eirea, Ph.D., Instituto de Ingenieria Electrica, Universidad de la Republica, Uruguay

A proposed new model for current-mode control retains the strengths of existing models such as ease of use and the ability to capture subharmonic oscillations, while improving on weaknesses like dc gain accuracy.

Current-mode control (CMC) is widely used in dc-dc converters for high-performance applications. In spite of its implementation simplicity, the dynamics are complicated and designing the control loop can be challenging. Many research efforts in the last two decades have refined dynamic models that capture the most relevant aspects of the controller behavior. Today's designers can choose from a vast pool of theoretical resources when developing a CMC solution.

A new model is being proposed that maximizes the advantages of the most popular model, while improving on its weaknesses. This model is based on already existing models but outperforms them in the design practice.

Eliminating Inductor Dynamics

The main idea behind CMC is that the inductor can be turned into a current source, thus eliminating the dynamics of the inductor in the loop.^[1] The controller sets a current reference and a fast inner-loop follows this reference cycle by cycle.

A typical implementation for a buck converter is shown in Fig. 1.^[2] This is the so-called peak CMC, because the inductor peak current follows the reference, as shown in the Fig. 2 waveforms. (Note that the inductor current shown in Fig. 2 corresponds to the sensed current, i.e., R_I × I_L) There is an outer voltage loop with an error amplifier that compensates for the dynamic response of the output voltage. The current loop is an inner loop that provides tight control on the peak inductor current.

There are similar architectures for average CMC and valley CMC, although they are not as popular.^[3-4] The compensation ramp shown in Fig. 1 is introduced to avoid subharmonic oscillations for duty cycles larger than 0.5.^[2] The slope of the compensation ramp (S_E in Fig. 2) plays an important role in the response of the system, as will be shown later.

Assuming that current tracking is perfect, the system effectively becomes a first-order model. The inductor current can be assumed to be equal to the reference current (V_C/R_I in Fig. 1). The control-to-output transfer function for a buck converter becomes:

where R_C is the ESR of the output capacitor.

Because this first-order transfer function is very easy to compensate, the design of the error amplifier is ideally simplified.

The assumption that current tracking is perfect is only valid for slow variations of the control signal, thus this model is only meaningful at low frequencies. If there is a need to push the bandwidth of the closed-loop system to frequencies above approximately one-tenth of the switching frequency, then a more detailed description of the dynamics of the current modulator is needed.

Over the years, many researchers have proposed models for CMC that take into account the dynamics at frequencies approaching the switching frequency.^[5-11] These models are developed under different assumptions about two main aspects of the loop dynamics.

The first assumption is the duty-ratio constraint that relates the duty cycle to the average values of the programmed current, the inductor current, the input voltage and the output voltage.^[12] Typical for this constraint are the use of a piecewise linear inductor waveform, in which the slopes may be constant or may change with the input and output voltages, and the definition of average inductor current, which can be computed as in steady-state or transient operation.

The second assumption is the sampling effect inherent to the modulation method. Typical for the sampling effect are the inclusions of either a fixed delay or a zero-order hold effect. It was noted that the modulator creates frequency components at the output that were not present at the input and that, for perturbations above one-tenth of the switching frequency, the additional components at the output are significant.^[12] This fact, together with the time-varying nature of the modulator, poses a warning against the validity of linear time-invariant (LTI) models for characterizing the behavior of the current loop at high frequencies. However, practice has demonstrated that LTI models are very useful for the design process, because they can capture enough information as to predict the stability and performance of the controller.

A unified model for different current-mode architectures and using general gain parameters was presented by Robert Sheehan of National Semiconductor (“A New Way to Model Current-Mode Control,” June 2007, Power Electronics Technology).^[13-14] The unified model is consistent with the general models derived and can be extended to emulated CMC using sampling and hold techniques.^{[8, 11]}

A very popular and widely accepted model was first introduced by Raymond B. Ridley (“A New, Continuous-Time Model for Current-Mode Control,” IEEE Transactions on Power Electronics, 1991, vol. 6, no. 2, pp. 271-280).^[8] That model is derived using a sampled-data analysis and takes into account the sampling effect of the modulator by introducing a zero-order hold. As a result, both low-frequency behavior and high-frequency subharmonic oscillations can be predicted. The inner current loop is then modeled as shown in Fig. 3:

where F_M is the modulator gain, S_N is the on-time slope of the sensed inductor waveform, namely R_I × V_I/L in a buck converter, S_E is the slope of the compensation ramp and T_S is the switching period.

where F_I is the approximate transfer function (ignoring parasitics and assuming the output voltage is constant) from the duty cycle to the inductor current and the sampling gain is:

A rational approximation of Eq. 4 can be computed using a Padé approximation of order (2, 2) of the exponential function.^[15] This is useful for analysis purposes and for using some simulation tools that only allow rational transfer functions. The resulting sampling-gain approximation becomes a two-zero function given by:

where ω_N = π/T_S and Q_Z = -2/π.

It has been noted in literature (Mayer and King, The University of Toledo) that some of the assumptions yield an inaccurate dc gain in the loop-transfer function.^{[8, 16]} This was confirmed in practice by the authors. In the following section, the source of this inaccuracy is identified and a new model with an accurate dc gain is proposed.

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