Phase Management Raises Interleaved PFC Efficiency

Jul 1, 2007 12:00 PM
By Michael O'Loughlin, Applications Engineer, Texas Instruments, Dallas

When the hysteretic comparator's output is high, the boost PFC pre-regulator runs in single-phase operation, and FET Q2 is always off. When the hysteretic comparator output (V4) is low, the gate-drive control signal from the PFC control (GD2) is passed through to the FETs gate drive. The interleaved PFC pre-regulator runs both phases.

Phase-management circuitry in Fig. 2 works in applications similar to the power converter in Fig. 1 by properly selecting resistor R3 and R5, based on the appropriate power levels. This is done by disconnecting the GD2 trace from the PFC controller to the gate driver 2 of Fig. 1. The circuit of Fig. 2 would be put in with the V_RS trace connected to the V_RS signal at R_S, and the GD2 output at the PFC connected to GD2 input of Fig. 2 and the Out1 signal of Fig. 2 connected to the input of the gate driver 2 of Fig. 1. The following example shows how to select these two resistors based on a 250-W power supply that has a regulated PFC boost voltage (V_BOOST) of 390 V. The current-sense resistor of the forward converter (R_S) in this example is 0.33Ω. The circuit turns the second boost phase off when the supply is operating at less than 29% of the converters rated output power. The second boost phase turns on when the converter is operating at greater than 32% of the supply's rated output power. The bias voltage (V_BIAS) was set to 12 V.

Resistor R3 determines the current-sense amplifier gain and is selected so that V2 will operate from a 0-V to 10-V range. For the circuitry to turn phase two on and off, the efficiency (η) of the second power stage needs to be considered. In this example, the efficiency of the second stage was 86%, and R3 needs to be 39 kΩ, based on load and the forward converter's efficiency.

Resistor R5 sets the approximate power level where phase two is disabled. In this example, resistor R5 was selected to turn the phase off at a power level of approximately 30% of the full load power (%Load).

A standard value resistor of 3.3 kΩ was chosen for R5. Eq. 8

Resistor R6 sets up the converter's hysteresis and may need to be adjusted for the individual application. In this example, the converter had roughly 288 mV of hysteresis. The second boost phase (phase two) turns on when the converter is operating at 32% of its rated output power. Phase two turns off when the converter is operating below 29% of the supply's rated output power.

To evaluate how well the circuitry worked, a simplified SPICE model was constructed and evaluated. The output power (P_OUT) was varied from 0 W to 250W and back down to 0 W over a 40-ms period. The output power (P_OUT) and the voltages at node V2, V3 and the gate of FETs Q1 (V_GQ1) and Q2 (V_GQ2) were monitored. Refer to Fig. 3 for waveforms.

This evaluation confirms that phase two turns on when the converter is loaded with greater than 32% of its maximum output power, and two turns off when the converter is loaded with less than 29% of the system's maximum output power. However, due to the delays caused by the low-pass filter of R1 and C1, phase two turns on at 82 W and turns off at 70 W. These values correspond to roughly 33% and 28% of the supply's rated output power. The delay is apparent in the offset of the peak of the P_OUT and V2 waveforms. The maximum time delay caused by the filter is less than 1.1 ms and has a minor effect on the simulated system.

An Integrated Approach

An alternative to implementing phase-management circuitry with discrete components is to integrate this functionality within the PFC controller. To illustrate this approach, a 300-W interleaved transition-mode PFC pre-regulator prototype was constructed (Fig. 4) using TI's UCC28060, an interleaved transition-mode controller with built-in phase-management circuitry.

In this design, both interleaved converter phases operate when the converter is loaded with more than 30% of the power converter's maximum output power.

Figs. 5 and 6 show the PFC pre-regulator prototype's efficiency with and without phase management at input voltages of 115 Vac and 230 Vac, respectively. These graphs show that phase management improved the light-load efficiency of the prototype by 1% to 3% based on line and loading. This efficiency improvement at light loads by phase management could be the difference between passing and failing the 80 PLUS light-load efficiency specification.

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