Phase Management Raises Interleaved PFC Efficiency

Jul 1, 2007 12:00 PM
By Michael O'Loughlin, Applications Engineer, Texas Instruments, Dallas

Eq. 3 describes the two-phase interleaved boost diodes and boost FETs switching losses, where V_DS and I_DS are the FET drain-to-source switching voltage and FET drain current, respectively. Variables t_R and t_F are the FET's drain-to-source rise and fall times. C_OSS is the FET's parasitic drain-to-source capacitance, Q_G is the FET's gate charge, and V_G is the gate-drive voltage applied to the FET's gate drive to activate it. Variable f_S represents the converter's switching frequency. Variable I_RR represents the boost diodes reverse-recovery current.

In these two-stage, off-line power converters, the front end (stage one) provides PFC. Generally, stage two is a forward converter that steps down the PFC boost voltage to a lower, more usable voltage. Since the PFC front end regulates the input of the forward converter, the average current-sense signal developed across the stepdown converter's current sense signal (R_S) can be used to monitor the average input power of the forward converter. This average current-sense signal can be then used to trigger phase-management circuitry.

The circuitry presented in Fig. 2 can be added to the system presented in Fig. 1, providing phase management to activate and deactivate PFC boost phases based on system loading. This circuitry replaces gate driver 2 block in Fig. 1. This circuitry works by using the current-sense signal developed across the forward converter's current-sense resistor (V_RS) to activate and deactivate phase two of the interleaved PFC pre-regulator (stage one).

In Fig. 2, resistor R1 and C1 form a low-pass filter with a low-frequency pole at 723 Hz. This filter is used to develop a dc voltage (V1) that represents the average voltage across the stepdown converter's current-sense resistor. Generally, since the average current-sense signal is less than 0.25 V, the noninverting amplifier configuration of electrical components A1, R3 and R2 is used to amplify the average current-sense signal (V1) to a more manageable voltage (V2) that can be easily monitored.

Amplifier A2 and electrical components R4, R5 and R6 form a hysteretic comparator that enables and disables phase two, based on the amplified average current-sense signal. Resistor R7 and R8 form a voltage divider to attenuate the output of amplifier A2. This helps to protect the gate driver IC U1. Gate driver U1 is a FET gate driver with an inverting and noninverting input that drives FET Q2. It can be activated and deactivated based on the output of the hysteretic comparator (V4).

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