Keeping Parts Cost Down in Mobile CPU Power Supplies

Oct 1, 2006 12:00 PM
By Tod Schiff, Senior Field Applications Engineer, Computing Segment, Analog Devices, Beaverton, Ore

Minimizing Output Capacitance

Ceramic and bulk capacitors perform different jobs at the output of a switching regulator. Ceramic capacitors take care of high-frequency transients at the CPU. Placing them inside the CPU socket provides best transient suppression, but this limits the number of capacitors that will fit. Additional capacitors, if needed, must be placed alongside the socket.

The worst-case transient is usually a maximum load step out of deep sleep. The switch's on-time, maximum output current step and maximum output slew rate all determine the required output filter at the CPU power pins. For most notebook applications, output capacitance should be at least 300 µF, which can be obtained by using 32 0805-sized 10-µF ceramic capacitors.

Variations in pc-board parasitics may change the amount of capacitance needed. Aside from their high cost and large size, simply throwing a lot of bulk capacitance at low-frequency output filtering won't work. On-the-fly voltage changes impose an upper limit — the supply must make a voltage step and settle with a specified error band within a given time. The output needs a minimum capacitance for smooth load release with the maximum load step ΔI_O and the maximum allowable overshoot — that's the lower limit.

With a maximum allowable overshoot V_OSMAX, the load release voltage is:

ΔV_O = ΔI_O × R_O + V_OSMAX.
(Eq. 2)

These equations define the limits on bulk capacitance (C_X):

where C_Z is the total output ceramic capacitance, V_V and t_V are the VID-on-the-fly output voltage change and response time, n is the number of phases, and K = -1n(V_ERR/V_V). In this last term, V_ERR represents the settling error.

To meet the equations, the effective series resistance (ESR) of the bulk capacitors should be less than twice the droop resistance (R_O). If the equations give a C_XMIN that's larger than the C_XMAX, either the inductor can be reduced or more phases can be added to meet the V_VID step requirement. Maintaining the same output ripple with a smaller inductor requires a higher switching frequency.

As an example, with C_Z = 320 µF, a 22-µs VID on-the-fly 220-mV step (t_V and V_V), a 27-mV overshoot limit and a 10-mV settling error, the bulk capacitors should be in the 1.1-mF to 2.1-mF range. Four 330-µF aluminum-poly capacitors, each with typical 6-mΩ ESR, gives a total of 1.32 mF total with 1.5-mΩ ESR. The effective series inductance (ESL) of the bulk capacitors should be low enough to limit high-frequency ringing during a load step. ESL ≤ C_Z × R_O² × Q², with Q² limited to 2 for a critically damped system.

If the ESL of the bulk capacitors is too large, either the number of ceramic capacitors can be increased or lower ESL bulk capacitors can be used.

MOSFET Choices

MOS power devices in buck supplies need low R_DSON to minimize conduction losses and power dissipation. They also need low input capacitance to minimize turn-on time. Faster devices with lower C_ISS have higher R_DSON, so a compromise is necessary. The gate drive is limited to 5 V by the MOSFET driver, so MOSFETs with logic-level thresholds are the only choice. Power dissipation from main and ripple currents dominates synchronous MOSFET power losses.

Synchronous MOSFETs can accidentally turn on if their reverse-transfer capacitance couples enough charge to the gate when the switch node goes high. This results in shoot-through with both main and synchronous devices on. Use a 1-to-10 or lower ratio of feedback capacitance to input capacitance in the synchronous devices to prevent it.

The turn-off time for the synchronous MOSFETs should be less than the nonoverlapping dead time of each phase's MOSFET driver. As an example, the ADP3419 MOSFET driver from Analog Devices has a 1.5-Ω output impedance and 45-ns typical dead time. Using MOSFETs with typical 1-Ω gate resistances and keeping the RC time constantly less than 45 ns gives an upper limit of 9000 pF on total gate capacitance. When using two parallel MOSFETs, the gate capacitance of each should be less than 4500 pF.

High-side MOSFETs need to handle power dissipation from conduction currents and switching losses. Switching losses come from turn-on and turn-off times, so the input capacitance of these FETs must be lower than that of the synchronous MOSFETs.

One more thing to check is the driver dissipation for each phase. The total of each driver's standby power plus the power needed to supply the gate charges should be less than the driver's dissipation limit at the highest ambient temperature. For SOIC packages operating up to 90°C pc-board temperature, 0.5 W of total dissipation gives a safe 120°C junction temperature.