Design Technique Models POL Performance

Apr 1, 2004 12:00 PM
By David Morrison, Editor, Power Electronics Technology

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The use of purchased dc-dc converter modules can simplify the implementation of board-level distributed power architectures (DPAs). However, when these modules are designed into a DPA, the interaction of multiple converters can affect converter stability and control loop performance. In particular, these issues must be addressed when designing an intermediate bus architecture, where an isolated dc-dc converter powers a series of nonisolated point-of-load converters (POLs).

Although existing techniques can assure the overall system stability and model the performance of the isolated converter, they don't predict the performance of the POLs. New techniques described in a paper at the recent Applied Power Electronics Conference enable designers to model the POLs, so they can design DPA systems without imposing overly conservative impedance ratios in their designs.

In “Accurate Loop Gain Prediction for Load DC-DC Converters in On-Board Distributed Power Systems,” Peng Li of Performance Motion Devices and Brad Lehman of Northeastern University describe how nominal small signal models (impedances and loop gains) of individual POLs can be used to forecast changes in POL loop gain when the POLs are incorporated into a DPA system.

Rather than attempting to model the whole DPA system, this technique only determines changes in POL performance. Furthermore, this approach allows the system designer to model any type of loop gain within the POL and predict how that loop gain changes when an arbitrary impedance, such as that of a particular dc-dc converter, is connected to the input of the POL.

The basis for this loop gain prediction technique is a Thevenin representation of the POL within the system. The figure depicts a generic DPA and the Thevenin equivalent of the nth POL converter in the system. In this example, T_Z is the POL's outer voltage loop gain, but any loop gain within the POL can be modeled. From this diagram, it can be seen that the impedance experienced by the POL at its input is the lumped impedance of the source dc-dc converter and the other POLs in the system. The Thevenin circuit also suggests that the control loop parameters (gain margin, crossover frequency and phase margin) can be determined for each POL. With this information in hand, designers can forego use of conservative design rules.

Li and Lehman explain how loop gain for an individual POL can be calculated. The basic equation for the loop gain shown in the figure is:

where Z is the impedance of the source dc-dc converter, Z_LN is the impedance of the nth POL, T_∞ is the loop gain when Z is infinite, and T₀ is the loop gain when Z is zero. In some cases, these values may be available from the POL supplier. Alternatively, they may be measured directly or indirectly using methods described by the authors.

In the case of the impedance values, Z and Z_LN, it's possible to forego separate impedance measurements and measure the needed ratio Z_LN /Z (also referred to as ß) by making in-system measurements. To do this, a small current can be injected at the node between the source dc-dc converter and the POL. The impedance ratio, Z_LN /Z, is then calculated as the ratio of the resulting voltages across the POL input and source dc-dc converter output.

When there are n POLs in the system, the ß for each POL must be measured to determine the loop gains of the individual POLs. Alternatively, system designers can obtain the impedance ratios by constructing small-scale prototypes, as described in one of the authors' previous publications.

For more information, contact the authors at peng@pmdcorp.com and lehman@ece.neu.edu.

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