Consider SEPIC Topology for New Designs

Nov 1, 2002 12:00 PM
By Thierry Rahban, Maxim Integrated Products, France

SEPIC topology exhibits advantages where a converter has a wide input voltage range.

A distinguishing characteristic of the SEPIC (single-ended primary inductance converter) topology is that its input voltage range can overlap the output voltage. For example, a Li-ion battery retains useful energy from 4.2V to 2.7V, so the input voltage to the associated converter can range above and below its output — eliminating the possibility of using an exclusively step-up or step-down configuration. SEPICs also find use in power factor corrected supplies where this topology can accept medium to low input voltages, providing the required output even if the peak input voltage is higher.

Boost topology (Fig. 1) is the basis for the SEPIC converter. First, switch SW closes during T_ON, increasing the magnetic energy stored in inductor L1. Next, the switch opens during T_OFF, offering D1 and C_OUT as the only path for stored magnetic energy to flow. C_OUT filters the current pulse generated by L1 through D1. When V_OUT is relatively low, you can improve the efficiency by using a Schottky diode with low forward voltage (about 400 mV) for D1. V_OUT must be higher than V_IN. In the opposite case (VIN > VOUT), D1 is forward biased, and nothing prevents current flow from V_IN to V_OUT.

The SEPIC circuit in Fig. 2, on page 19, removes this limitation by inserting a capacitor (C_p) between L1 and D1. This capacitor blocks any dc component between the input and output. However, D1's anode must connect to a known potential. This is accomplished by connecting D1 to ground through a second inductor (L2). L2 can be separate from L1 or wound on the same core, depending on the application's needs. Because the latter configuration is simply a transformer, a classical flyback topology may be more appropriate in that case. However, the transformer leakage inductance, which is no problem in SEPIC configurations, often requires a “snubber” network in flyback topologies. The main parasitic resistances R_L1, R_L2, R_sw, and R_cp are associated with L₁, L₂, S_w, and C_p, respectively.

Although it has very few elements, the operation of a SEPIC converter isn't so simple to abstract into equations. We assume that the values of current and voltage ripple are small with respect to the dc components. To start, we express the fact that at equilibrium there is no dc voltage across the inductors L1 and L2 (neglecting the voltage drop across their parasitic resistances). Therefore, C_p sees a dc potential of V_IN at one side, through L1, and ground on the other side, through L2. Thus, the dc voltage across C_p is:

(V_cp)_mean = V_IN (1)

“T” is the period of one switching cycle. Call α the portion of T for which Sw is closed, and 1-α the remaining part of the period. Because the average voltage across L1 equals zero during steady-state conditions, the voltage seen by L1 during αT (T_ON) is exactly compensated by the voltage seen during (1-α)T (T_OFF): (2)

αTV_IN = (1-α)T(V_OUT + V_d + V_cp - V_IN) = (1-α)T(V_OUT + V_d)

V_d is D1's dc forward voltage drop for (I_L1 + I_L2), and V_cp equals V_IN:

(V_OUT + V_d)/V_IN = α/(1-α) = A_i (3)

A_i is called the amplification factor, where “i” represents the ideal case when parasitic resistances are null. Neglecting V_d with respect to V_OUT (as a first approximation), we see the ratio of V_OUT to V_IN can be greater than or less than 1, depending on the value of α (with equality obtained for α = 0.5). This relationship illustrates the peculiarity of SEPIC converters with respect to the classical step-up or step-down topologies. The more accurate expression A_a accounts for parasitic resistances in the circuit:

Equation (4) lets you compute the minimum, typical, and maximum amplification factors for V_IN (A_amin, A_atyp, and A_amax). The equation is recursive (“A” appears in both the result and the expression), but a few iterative calculations lead to the solution asymptotically. The expression neglects transition losses due to switch Sw and reverse current in D1. Those losses are usually negligible, especially if Sw is a fast MOSFET and its drain-voltage excursion (V_IN + V_OUT + V_d) remains under 30V (the apparent limit for today's low-loss MOSFETs).

In some cases, you should also account for losses due to the reverse current of D1 and for core losses due to high-level induction gradients. You can extrapolate the corresponding values of α from Equation (3):

α_xxx = A_axxx/(1+A_axxx), where xxx is min, typ, or max. (5)

The dc current through C_p is null, so the average output current can only be supplied by L2:

I_OUT = I_L2 (6)

L2's power dissipation requirement is eased, because the average current into L2 always equals I_OUT and does not depend on variations of V_IN. To calculate the current into L1 (I_L1), express the fact that no dc current can flow through C_p. Thus, the coulomb charge flowing during αT is perfectly balanced by an opposite coulomb charge during (1-α)T. When the switch is closed (for an interval αT), the node A potential is fixed at 0V. According to Equation (1), the node B potential is -V_IN, which reverse-biases D1. Current through C_p is then I_L2. When the switch is open during (1-α)T, I_L2 flows through D1 while I_L1 flows through C_p:

αT × I_L2 = (1-α)T × I_L1 (7)

I_L2 = I_OUT, so:

I_L1 = A_axxx × I_OUT (8)

Because input power equals output power divided by efficiency, I_L1 depends strongly on V_IN. For a given output power, I_L1 increases if V_IN decreases. Knowing that I_L2 (hence, I_out) flows into C_p during αT, we choose C_p so that its ripple ΔV_cp is a very small fraction, γ, of V_cp (γ = 1% to 5%). The worst case occurs when V_IN is minimal.

C_p ≥ I_OUT α_min T/(γ V_IN(min) (9)

The combination of high-frequency controller operation and recent progress in multilayer ceramic capacitors (MLCs) allows the use of small-size, nonpolarized capacitors for C_p. Be sure that C_p can sustain the power dissipation P_cp due to its own internal resistance (R_cp):

P_cp = A_amin R_cp I_OUT² (10)

R_SW, consisting usually of the MOSFET switch drain-to-source resistance in series with a shunt for limiting the maximum current, incurs the following loss:

P_SW = A_amin (1 + A_amin) R_SW I_OUT² (11)

Losses P_rL1 and P_rL2 due to the internal resistances of L1 and L2 are easily calculated:

P_rL1 = A_amin² R_L1 I_OUT² (12)

P_rL2 = R_L2 I_OUT² (13)

When calculating the loss due to D1, take care to evaluate V_d for the sum of I_L1 + I_L2:

P_D1 = V_d × I_OUT (14)

L1 is chosen so its total current ripple (ΔI_L1) is a fraction (β = 20% to 50%) of I_L1. The worst case for β occurs when V_IN is maximum, because ΔI_L1 is maximum when I_L1 is minimum. Assuming β = 0.5:

L1_min = 2 T (1-α_max) V_IN(max)/I_OUT (15)

Choose a standard value nearest to that calculated for L1, ensuring its saturation current meets the following condition:

I_L1(sat) >> I_L1 + 0.5 ΔI_L1 = A_amin I_OUT + 0.5 T α_min V_IN(min)/L1 (16)

The calculation for L2 is similar to that for L1:

L2_min = 2 T α_max V_INmax/Iout (17)

I_L2(sat) >> I_L2 + 0.5 ΔI_L2 = I_OUT + 0.5 T α_max V_IN(max)/L2 (18)

If L1 and L2 are wound on the same core, you must choose the larger of the two values. A single core compels the two windings to have the same number of turns and, therefore, the same inductance values. Otherwise, voltages across the two windings will differ and Cp will act as a short circuit to the difference. If the winding voltages are identical, they generate equal and cumulative current gradients. Thus, the natural inductance of each winding should equal only half of the value calculated for L1 and L2.

You can save costs by winding them together in the same operation. If the windings' cross-sections are equivalent, the resistive losses will differ because their currents (I_L1 and I_L2) differ. However, total loss is lowest when losses are distributed equally between the two windings — so, it's useful to set each winding's cross-section according to the current it carries. This is easy to do when the windings consist of split wire for counteracting skin effects. The core size is chosen to accommodate a saturation current much greater than (I_L1 + I_L2 + ΔI_L1) at the highest core temperature anticipated.

The purpose of the output capacitor (C_OUT) is to average the current pulses supplied by D1 during T_OFF. The current transitions are brutal, so C_OUT should be a high-performance component like the one used in a flyback topology. Today's ceramic capacitors provide low ESR and ESL. The minimum value for C_OUT is determined by the amount of ripple (ΔV_OUT) that can be tolerated:

C_OUT >= A_amin I_OUT α_min T/ΔV_OUT (19)

The value of an actual output capacitor may need to be much larger, especially if the load current is composed of high-energy pulses. The input capacitor can be very small, thanks to the filtering properties of the SEPIC topology. Usually, C_IN can be 10 times smaller than C_OUT:

C_IN = C_OUT/10 (20)

Overall efficiency η can be predicted from V_IN and A_a. However, the result can be optimistic, because it doesn't account for the switch-transition losses and core losses:

η = V_OUT/A_a V_IN (21)

The switch SW and diode D1 should be rated for breakdown voltages respectively greater than V_DS and V_R:

V_DS > 1.15(V_OUT + V_d + V_IN) (22)

V_R > 1.15(V_OUT + V_IN) (23)

For example, consider component ratings in the following low-power application: V_IN(min) = 2.7V, V_IN(typ) = 3.5V, and V_IN(max) = 5V, for V_OUT = 3.8V, I_OUT = 0.38A, T = 2 µs, and V_d = 0.4V. A round of initial estimates gives the following approximate values: L1 and L2 = 47 µH, R_L1 = R_L2 = 120mΩ, R_cp = 50mΩ, and R_SW = 170mΩ. Fig. 3 shows the resulting I_L1 and I_L2 waveforms at different V_IN values.

Using Equation (3), you first calculate the ideal amplification factors Ai corresponding to minimum, typical, and maximum V_IN as 1.555, 1.2, and 0.84. Using these values in Equation (4), you obtain the more accurate A_axxx values of 1.735, 1.292, and 0.88, respectively. The corresponding duty cycles are deduced from Equation (5) as 0.634, 0.563, and 0.468.

The L2 current (I_L2) equals 0.38A according to Equation (6), and I_L1 varies according to V_IN. Using Equation (8), we obtain IL1 values of 0.659A, 0.491A, and 0.334A as VIN varies from minimum to maximum.

We obtain a minimum C_p value of 3.5 µF by fixing γ = 5% in Equation (9). The voltage rating of C_p is deduced from Equation (1). If the input voltage is not to exceed 5V, a 6.8-µF ceramic capacitor rated at 6.3V should do the job. Modern MLC capacitors easily meet the expected 50mΩ R_cp, and they easily sustain the 12.5-mW power loss deduced from Equation (10).

The following parameters are computed at the worst case, which is minimal V_IN:

• A 170mΩ switch must dissipate 116.5mW according to Equation (11), which allows the external transistor to be an SOT23 package, or even the smaller SC70.
• Equations (12) and (13) give losses of 52.2mW and 17.3 mW for L1 and L2. We verify here that the copper cross-section of L1 should be larger than that of L2.
• Using Equation (14) to calculate the power loss of D1 at 152 mW, we see that D1 is the main source of loss. Therefore, it's important to choose an efficient rectifier or a synchronous rectifier.
• For L1, Equation (15) suggests a minimum value of 28 µH, which is close to the estimated value of 47 µH. For normal operation with an L1 value of 47 µH, Equation (16) predicts a peak current of 0.69A. A device rated at 1A provides a reasonable margin. Make sure D1 can sustain current pulses at high temperature equal to I_L1 + I_OUT = 1.04A, and an average current, I_OUT = 0.38A.
• Similarly, Equation (17) leads to a minimum L2 value of 24.6 µH. Again, 47 µH is a reasonable value. According to Equation (18), L2 should sustain current peaks of 0.43A.
• For ΔV_OUT (V_OUT/100) of 38mV, Equation (19) says the output capacitor should be at least 22 µF. Equation (20) says 2 µF should be sufficient for C_IN.
• Despite high-valued parasitic components, Equation (21) predicts a respectable efficiency of 81% for the worst case, in which input voltage is minimum. When considering transition losses, the actual value is lower.

Fig. 4 shows a SEPIC converter realized with the component values calculated above and the MAX669 PWM controller IC switching at 500 kHz. Use of the MAX669, which comes in a 10-pin mmax package — along with a tiny power switch and inductors — reduces p.c. board space. This SEPIC converter's efficiency was measured with a 4.1V input (a nominal Li-ion battery voltage) and a 3.8V output, from which 380mA was drawn. Fig. 5 shows that this regulator achieves an acceptable 84.5% efficiency at the nominal load, despite the use of the tiny power switch and inductors previously mentioned.

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