Improved MOSFET Model Achieves Higher Accuracy

Jan 1, 2007 12:00 PM
By Scott Pearson, Modeling Engineer, Sylvie Tran, Product Modeling Engineer, and Steven Sapp, Produc

BSIM3 SPICE MOSFET Model

From inception, device models in SPICE were designed to be scaled, thus enabling chip-level modeling of circuits comprised of different size transistors. The process features — such as gate-oxide thickness, channel length and channel-doping concentration — define the device performance. With all the process features being common, channel width alone would then determine the I-V characteristics of the MOSFET in the simulated IC.

As evidenced by the macro-model approaches discussed previously, power MOSFET suppliers have struggled to represent the I-V and C-V characteristics of this class of device with a simple standard SPICE MOSFET model. Resorting to various methods to enable voltage-dependant capacitance and switching, these models cannot readily take advantage of the transistor-size-scaling capabilities of SPICE and tend to suffer from increased simulation time and convergence errors.

In this work, every effort has been made to overcome the scaling limitations of the previous model configurations, while at the same time providing excellent I-V and C-V correlation to characterization data. At the time of this writing, only trench-gate MOSFET structures have been built using the model described here. Planar-gate vertical double-diffused MOSFET (VDMOS) power devices have the additional complication of a parasitic JFET-like structure in the drift region current path, which may complicate the application of this simplified model.

It turns out to be relatively easy to define trench-gate VDMOS device features analogous to the architectural elements of the basic MOSFET structure on which the BSIM3 MOSFET model is based. When a representative half-cell cross section is rotated to show the gate in a horizontal direction more recognizable to those familiar with CMOS devices, the source, drain, gate and substrate (body) elements can more easily be related to their lateral MOSFET counterparts (Fig. 2). The magenta elements are conductors, so it should be clear that the source and the source-substrate contacts occur along the left vertical edge of the drawing, while the drain contact (not shown) would be on the right vertical edge.

With the trench MOSFET device features now mapped to equivalent lateral MOSFET structures, specific BSIM3 MOSFET model parameters can be determined for both I-V and C-V equations in SPICE. While outside the scope of this work, the BSIM3 MOSFET model parameters are defined and explained in great detail in other references.[2] By way of example, the BSIM3 parameter representing the overlap area between the source and the gate (CGSO) can be determined from the process and by device and process simulation. Similarly, the other BSIM3 MOSFET model parameters can be determined from the process and device features.

Having defined the trench MOSFET model only by parameters based on process and device features, the scalability of the device model in SPICE is restored. While it is beyond the scope of this overview, because the model parameters are based entirely on process and device features, knowing the process variation of those features enables the application of Monte Carlo circuit variability simulations. The restored scalability of the device model also allows product definition studies for sizing of the trench power MOSFET for optimum performance in the power application circuit.

One aspect the BSIM3 MOSFET model does not simulate is the breakdown voltage[2] that is enabled in our model by subcircuit components EBREAK, DBREAK, RBREAK and IT (Fig. 3). The voltage-controlled voltage source, EBREAK, when coupled with RBREAK and IT, determines low current avalanche breakdown voltage. The thermal compensation elements, TC1 and TC2, of RBREAK correct the temperature dependence of the low current breakdown. High current breakdown and the associated temperature dependence are accounted for by the series resistance and thermal coefficients of DBREAK.

The resistor RDRAIN corrects for the nonsilicon temperature-dependant effects on drain-source resistance. Without RDRAIN, the on-resistance dependence on temperature would be linear as opposed to an increasing ratio with temperature.

Other elements have been included in the subcircuit model to improve the accuracy of the switching simulation. RGATE is a lumped representation of the distributed gate resistance, while LDRAIN, RLDRAIN, LSOURCE, RLSOURCE, LGATE and RLGATE account for the package parasitic impedances.

The BSIM3 MOSFET model does not provide for any direct connection between the gate and the source terminals.[2] As a result, there is no leakage current from the gate to the source. The gate leakage current can be modeled by adding a large-value resistor between the gate and source, but is not included in our subcircuit model.

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© 2007 Penton Media, Inc.