W-Gated Trench MOSFET Offers Efficient DC-DC Converters

Sep 1, 2003 12:00 PM
By Mohamed Darwish, Vishay Siliconix, Santa Clara, Calif.

The new W-gated Trench MOSFET offers better trade-off between on-resistance and gate-drain capacitance.

Power demands of computing and telecom applications are driving rapid developments in semiconductor components for power conversion. By looking at next-generation microprocessor requirements — a higher load current slew rate of 2A/ns, an operating frequency of multi-GHz, and a lower input voltage of about 1V — it's easy to see the need for efficient dc-dc conversion.

Optimized W-gated Trench MOSFETs (WFETs) are answering the call. These devices achieve a control switch with a low silicon R_DS(on)×Q_gd figure of merit of 10.5mΩ×nC and a synchronous switch with a low gate-drain to gate-source ratio (Q_gd/Q_gs) of 0.45. Higher efficiency is possible when the WFET is used as the control and/or synchronous MOSFET in a synchronous buck converter circuit.

The synchronous buck converter is the most commonly used power stage for the distributed power architecture, The converter in Fig. 1 uses a high-side control switch (Q1), a low-side synchronous switch (Q2), and L and C as a filter. The power losses of the MOSFETs in a buck converter are the components that determine efficiency performance.

The MOSFET of choice for the control and synchronous switches is the trench-gated U-groove MOSFET (UMOSFET)becaue of its ultra-low on-resistance. Lower on-resistance is normally achieved by using higher cell density trench MOSFETs. This presents a challenge in scaling a conventional UMOSFET since its structure suffers from an inherent high gate-drain or Miller capacitance C_rss, as shown in Fig. 2. Because capacitance and on-resistance scale differently, a further increase in UMOSFET cell density is accompanied by a higher increase in C_rss, which degrades device switching performance. Fig. 3 shows the measured product of on-resistance and gate-drain charge R_DS(on)×Q_gd for a conventional trench MOSFET. A device with a 30V breakdown voltage exhibits a minimum R_DS(on)×Q_gd value of 35 mΩ×nC at a cell pitch of 2.5µm. Further reductions of the cell pitch below 2.5µm result in an undesirable increase in the R_DS(on)×Q_gd figure of merit. So, designers are faced with a trade-off between lower on-resistance and higher capacitance.

The new W-shaped gate trench MOSFET (WFET) addresses this dilemma. The WFET shown in Fig. 4 uses a thin gate oxide along the vertical walls and a thicker oxide at the bottom of the trench. The improvement over state-of-the-art structures is achieved by shaping the gate such that the thicker gate oxide at the bottom of the trench is self-aligned to the P-body/N-epi junction with a gradual transition to a thinner oxide along the trench walls and corners, resulting in a W-shaped gate. A slightly deeper P-body junction than the trench depth results in a lower capacitance as the source-drain voltage starts to increase. The result is a device that combines low specific on-resistance and low switching losses — which translates directly into higher efficiency when the WFET is used as the control and/or synchronous MOSFET in a synchronous buck converter circuit.

In a synchronous buck converter, the power losses in the control MOSFET are given by Equation 1 and are the sum of the losses due to conduction, switching, gate drive, and the loss associated with the output charge:

P_loss (control) = P_conduction (R_(DS),I_rms) + P_switching (Q_gs,Q_gd,V_in,f) + P_drive (Q_g,V_g,f) + P_output (Q_oss,V_in,f)

(Eq. 1)

The requirement to minimize conduction losses has driven further reductions in specific on-resistance and the increase in cell density or scaling cell pitch. However, reducing switching and drive losses requires minimizing gate-drain capacitance C_rss or gate-drain charge Q_gd and total gate charge Q_g. This is why both types of losses are combined in the figure of merit R_DS(on)×Q_gd used to benchmark the performance of the control MOSFET. For the synchronous MOSFET, power losses are given by Equation 2 and are due to conduction, gate drive, output, and losses associated with the body diode reverse recovery:

P_loss (synchronous) = P_conduction (R_ds,I_rms) + P_drive (Q_g,V_g,f) + P_output (Q_oss,Q_rr,V_in,f)

(Eq. 2)

where Q_rr is the body diode reverse-recovery stored charge. For the synchronous MOSFET, the dominant component in power loss is conduction losses. Furthermore, the body diode conduction during the dead time period results in a stored charge Q_rr. To turn Q2 off, the stored charge Q_rr needs to be removed, which results in power losses. Moreover, shoot-through or a high CdV/dt effect may cause an additional power loss due to an undesired turn-on of the synchronous MOSFET.

As you can see from Fig. 1, a rapid change in the drain voltage of Q2, resulting from the turn-on of Q1, may result in the turn-on of Q2. To avoid this effect, the ratio of Q_gd/Q_gs and gate resistance R_G of the synchronous MOSFET should be minimized for a specific threshold voltage V_th.

WFET Optimization

Control MOSFET : As a control switch, the WFET has a low R_DS(on)×Q_gd figure of merit. This is a result of the significant reduction in WFET C_rss compared to a conventional device. A WFET with sidewall and bottom gate oxide thickness of 50 nm and 150 nm, respectively, at V_DS = 0V/30V results in C_rss = 207 pF/89 pF compared to 762 pF/163 pF of a conventional device having the same active area and cell pitch as shown in the table. Similarly, Q_gd drops to 1.6 nC compared 4.5 nC, as shown in Fig. 6. The effect of cell pitch on the figure of merit R_(DS)on×Q_gd is shown in Fig. 6. The data shown are for WFET devices with different sidewall gate oxide thickness of 30 nm and a bottom oxide thickness 150 nm. An increase in the cell pitch from 2.4µm to 4.2µm results in the silicon R_DS(on)×Q_gd dropping from 12.5 mΩ.nC to about 10.5 mΩ.nC for the 30-nm device. This is due to the lower R_(DS)on for the same Q_gd since the bottom oxide thickness and the channel width are the same.

WFET Synchronous MOSFET: You can also optimize the WFET for use as a synchronous switch. Using the 2.4µm cell pitch, a high cell density greater than 100M cells/in² can be achieved. For a WFET with a cell pitch of 2.4µm and sidewall and bottom gate oxides of 50 nm and 180 nm, respectively, the specific on-resistance is 22 mΩ.mm². The device also shows a low Q_gd/Q_gs ratio, which is important for minimizing power losses due to shoot-through. The measured Q_gd/Q_gs ratio of a conventional PWM-optimized trench MOSFET drops from 0.8 to 0.45 for a WFET. Fig. 8 shows the same effect as an improvement in C_rss to the input capacitance C_iss ratio for a WFET with sidewall and bottom gate oxide thickness of 30 nm and 150 nm, respectively. This improvement can be used to optimize other device parameters. For the same level of shoot-through immunity, a lower threshold voltage can be used. This approach results in reduced conduction losses and lower total power loss.

Synchronous Buck dc-dc Converter Efficiency: The efficiency vs. output current of a PWM switch-mode, synchronous, 4-four-phase, dc-dc buck converter with 19V V_IN and 1.3V V_OUT using new optimized WFET switches is shown in Fig. 9. Using a switching frequency of 300 kHz, more than 90.9% efficiency can be achieved. Efficiency at a full load of 80A exceeds 85.5 % which is about 2% higher efficiency than the previous generation.

The WFET Advantage

The trade-off between on-resistance and gate-drain capacitance in WFET provides improved control and synchronous switch characteristics. With optimized devices achieving a control switch with a low silicon R_DS(on)×Q_gd figure of merit of 10.5 mΩ.nC and a synchronous switch with a low gate-drain to gate-source ratio (Q_gd/Q_gs) of 0.45, its advantages are significant.

For more information on this article, CIRCLE 335 on Reader Service Card