Optimizing Voltage Selection in Buck Converters

Jun 1, 2005 12:00 PM
By Alan Elbanhawy, Director, Computing and Telecommunications Segments, Advanced Power Systems Cente

Understanding the impact of input voltage and gate-drive voltage on MOSFET power losses enables designers to achieve maximum efficiency in the design of synchronous buck converters.

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For several years, the dc-dc converters used to power microprocessor core supplies in PCs have been fed by a 12-V source. This voltage was chosen to limit the current carried through the harness of the ATX power supply as well as limit the maximum current in the ATX output rectifiers. Although this rationale makes sense with regard to the ATX supply, it is contrary to the requirements of the core supply — typically a synchronous buck converter — on the motherboard. That's because dynamic losses in the buck converter rise in proportion to input voltage. Hence, the higher the input voltage, the lower the buck converter's efficiency.

Laboratory experiments show that both the input voltage and the gate-drive voltage play a major role in power loss in both the control or high-side (HS) MOSFET and the synchronous rectifier or low-side (LS) MOSFET, although to varying degrees. In this article, we will explore these effects and formulate the governing equations, and investigate the effects of different parameters on the converter's power losses.

A brief examination of the synchronous buck converter's circuit reveals the dynamic losses may be calculated from:

From this equation, we can see that this loss mechanism is directly proportional to input voltage (V_IN), the load current, which is approximately the MOSFET drain current (I_D), and the switching frequency (F_S). Therefore, the smaller any one of these parameters, the smaller the dynamic losses. The other major loss mechanism is conduction losses, which may be calculated for the HS MOSFET from the equation:

where Δ is the duty cycle:

The smaller the input voltage, the larger the conduction losses for the same MOSFET on-resistance (R_DS(ON)). Clearly, there is a point when the input voltage has a value where the combined dynamic and conduction losses are at a minimum, and this point is of particular interest to us because it represents the point of highest efficiency for the core supply.

The effect of the gate-drive voltage is more complex because it involves the nonlinear relationship between the gate-drive voltage and the MOSFET on-resistance. By driving the MOSFET at the right drive level, R_DS(ON) may be reduced by more than 50% from that of the nonoptimum gate-drive conditions.

We conducted two sets of tests: one to verify the effect of the input voltage on losses and efficiency and the other to verify the effect of the gate-drive voltage on the same efficiency and losses.

Fig. 1 depicts a voltage regulator module (VRM) efficiency as a function of the input voltage at different load currents. Given the typical 1.5-V VRM output voltage, optimum efficiency is achieved at an input voltage of 7 V to 8 V, not at the current 12 V. In this particular situation, an entire four percentage points in efficiency may be gained at full load, and considering that at this point the total losses are only 16 percentage points (100%-84%), this gain represents a 25% reduction in the converter los ses, a very sobering fact.

Fig. 2 depicts the efficiency of a different 1.5-V output VRM as a function of the gate-drive voltage showing that an efficiency increase of about 3% may be gained when operating at the optimal gate-drive voltage as compared to driving at the conventional 12 V.

Fig. 3 shows the effective loss resistance (R_OL)^[9] of the same converter in Fig. 2 as a function of the gate drive at different load currents. At full load, from 4.7-mΩ down to 3.9-mΩ, a gain of 17% can be achieved.

Fig. 4 shows the gains that may be attained at different load currents by optimizing the gate drive individually at each point.

Mathematical Representations of the Losses

First, we will derive formula to calculate the input voltage that delivers the highest power efficiency of a buck converter. To begin, consider the power dissipation relationship with input voltage for the top MOSFET. The power dissipation equation for the top MOSFET is as follows:

where T_R and T_F are the rise and fall times, respectively; V_IN is the input voltage; I_D is the load current; F_S is the switching frequency; R_DS(ON) is the MOSFET on-resistance; V_O is the output voltage; and V_O/V_IN is the duty cycle.

Assuming that T_R=T_F, we get:

(Note that we have ignored the losses due to the MOSFET output capacitance (C_OSS) because this term plays a secondary role in the power dissipation and it would complicate the solution immensely.)

Taking the first derivative of P_D with respect to V_IN, we get:

Then, taking the second derivative with respect to V_IN yields:

The second derivative is positive, indicating a minimum for power dissipation.

Solving Eq. 1 for the optimum input voltage (V_INOPT), we get:

where R_DS(ON)T is the top MOSFET's on-resistance. For an example calculation of V_INOPT, assume the following parameters: V_O = 1.7 V, V_IN = 12 V, T_R = 15 ns, and R_DS(ON)T = 0.012 Ω. Plotting the optimal input voltage (V_INOPT) versus drain current for switching frequencies of 300 kHz, 500 kHz and 1 MHz, we get the results graphed in Fig. 5.

Now, consider the power dissipation relationship with input voltage for the bottom MOSFET.

The power dissipation equation for the bottom MOSFET is as follows:

where R_DS(ON)B = bottom MOSFET on-resistance.

Taking the first derivative with respect to V_IN:

Now, taking the second derivative:

The second derivative is negative, indicating a maximum as V_IN approaches infinity. This clearly indicates that losses in the synchronous rectifier do not have a minimum as a function of V_IN.

Next, let's consider both the top and the bottom MOSFETs' losses together and attempt to find the optimum input voltage that would result in minimum losses, and hence, highest efficiency for the buck converter.

The equation for the combined losses in the top and bottom MOSFETs is:

Taking the first derivative of Eq. 2, we get:

Solving for V_IN yields two solutions:

and taking the positive solution leaves:

For an example using this equation, assume that V_O=1.7 V, V_IN=12 V, T_R=15 ns, R_DS(ON)T=0.01 Ω, and R_DS(ON)B=0.006 Ω. Once again, let us represent this equation in a graph form at switching frequencies of 300 kHz , 500 kHz and 1 MHz to derive the data plotted in Fig. 6.

Next, let us consider the dependency of power dissipation on the gate-drive voltage. Assume that the relationship between R_DS(ON) and V_G is linear for simplicity:

R_DS(ON)V_G = R_DS(ON) - BV_G

where V_O is the amplitude of the gate-driver output voltage and B is a constant.

Assume that V_O=1.7 V, F_S=1×10⁶ Hz, T_R=15×10^-9 sec, and C_IN=5×10^-9 F. Then, substituting in the equation for two points at V_G=5 V and 10 V.

0.100 = R_DS(ON) - B·5 (Eq. 3)

0.008 = R_DS(ON) - B·10 (Eq. 4)

Solving Eq. 3 and Eq. 4 for R_DS(ON) and B:

Solving Eq. 5, we get:

R_DS(ON)=0.012 Ω and B=4 × 10^-4

The duty cycle (Δ) may be calculated according to this equation:

Let us consider the losses in the top MOSFET:

where C_IN=total input capacitance measured at the gate of the MOSFET, including the Miller capacitance.

Taking the first derivative of P_D with respect to V_G,

Now, solving Eq. 6 for the optimum gate-drive voltage V_G, we get:

Now, let's consider the bottom MOSFET given that V_IN=12 V and Δ=1-(V_O/V_IN). In this case:

Taking the first derivative of P_D with respect to V_G yields:

Now, solving for Eq. 6 the optimum gate-drive voltage V_G, we get:

Next, let's consider the situation where we determine one optimum gate-drive voltage for both the top and bottom MOSFETs:

0.012=R_DS(ON)T - B·5

0.010=R_DS(ON)T - B·10

0.008=R_DS(ON)B - B_B·5

0.006=R_DS(ON)B - B_B·10

The total power dissipation of both the top and bottom MOSFETs is:

where B_T and B_B are the coefficients of the equation for R_DS(ON) as a function of V_G, and R_DS(ON)T and R_DS(ON)B are the other coefficients of the top and bottom MOSFET, respectively.

Taking the first derivative with respect to V_G:

Then, taking the second derivative:

Now, solving the first derivative equation yields:

Assume that C_INT = 2.2×10^-9 F and C_INB = 4×10^-9 F. Then once again we may represent the equation for optimum gate-drive voltage in graphic form for switching frequencies of 300 kHz, 500 kHz and 1 MHz, as shown in Fig. 7.

Finally, using the equations derived previously, Fig. 8 depicts the optimum input voltage as a function of the load current ID and the switching frequency F_S. Examination of the graph shows that the optimum input voltage for high frequency high current has a value of about 4 V to 6 V, a far cry from the current 12 V. Fig. 9 depicts the gate-drive voltage again as a function of I_D and F_S and clearly shows that higher currents require higher drive voltage, while higher frequency requires lower drive voltage for optimum power loss.

Several conclusions can be drawn from the experiments described here. We have shown in Figs. 5 and 6 that the optimal input-source voltage is not 12 V, but rather in the neighborhood of 3 V to 5 V, depending on the load current and the switching frequency. The larger current drawn from a 5-V source compared to a 12-V one can easily be dealt with through proper motherboard layout. Unfortunately, the off-line power-supply (silver-box) manufacturers have championed the push for higher source voltage because this allows them to continue using cheaper rectifiers instead of synchronous rectifiers. This savings results in lower-efficiency dc-dc converters and aggravates the thermal management problem in PCs.

We also have shown that the gate-drive voltage has an optimal value. This could be accommodated by PWM controller manufacturers giving the end customer the choice of gate-drive voltage.

The optimal gate-drive voltage, as seen from Eq. 7 and Eq. 9, is inversely proportional to the switching frequency and directly proportional to the square of the load current. There is no optimal source voltage for the synchronous rectifier on its own since a larger input voltage means longer on-time for the synchronous rectifier and hence more power dissipation.

References

1. Elbanhawy, Alan. Effect of Parasitic Inductance on switching performance. Proc. PCIM Europe 2003, pp. 251-255.

2. Elbanhawy, Alan. Effect of Parasitic Inductance on Switching Performance of Synchronous Buck Converter. Proc. Intel Technology Symposium 2003.

3. Elbanhawy, Alan. Mathematical Treatment for HS MOSFET Turn Off. Proc. PEDS 2003.

4. Elbanhawy, Alan. A Quantum Leap in Semiconductor Packaging. Proc. PCIM China, pp. 60-64.

5. Alan Elbanhawy. The Road to 200 Amps at one Volt VRM. Proc. PCIM Europe 2004, pp. 54-58.

6. Elbanhawy, Alan and W. Newberry. Packaging Parasitic Resistance Frequency Effects. Power Electronics Conference USA 2004 PCIM San Francisco.

7. Elbanhawy, Alan, and J. Ejury. Investigations of the Influence of PCB Layout Parasitic Inductances in DC/DC Converters on the Efficiency. Proc. PCIM Europe 2004, pp. 31-36.

8. Elbanhawy, Alan. Are Traditional Packages Suitable for the New Generation of DC-DC Converter? Proc. IPEMC China 2004.

9. Elbanhawy, Alan. Is the Power Conversion Efficiency Running Out of Steam as a Comparison Tool? Proc. Portable Power Developer Conference USA 2005.