The J/K Method: A Technique to Select the Optimal MOSFET

Jun 1, 2010 12:00 PM
PETER JAMES MILLER Applications Engineer, Texas Instruments, Dallas, TX

Looking through TI's NexFET™ devices, we find a likely candidate, the CSD16412Q5A with RDS(ON) = 13mΩ and Qsw = 1.4nC (ratio = 9.29).

Select equations to enlarge.

J and K are calculated for the low-side MOSFET as follows:

Again reviewing TI's NexFET™ devices, we find the CSD16407Q5 with RDS(ON) = 2.5mΩ and Qsw = 6.15nC (ratio = 0.41).

J/K SELECTION WITH DUAL MOSFETS

Sometimes you may want to either select the same MOSFET for both the high-side MOSFET and low-side MOSFET or to use a dual device with both MOSFETs in a single package. With very different J/K ratios for the high-side and the low-side, how does one select the most efficient MOSFET within this constraint? While averaging the two J/K ratios may seem like a straight-forward solution to this issue, it ignores a bias towards the MOSFET dissipating more power. Instead, the J and K values of both the high-side and low-side MOSFETs should be summed before the ratio is calculated. This weights each MOSFET proportional to its total power loss, thus balancing the total switching losses with the total conduction losses for the most efficient result.

Using the same design above, but limiting the selection to using the same MOSFET for both high-side and low-side, the optimized J/K ratio would be:

(See equation 11)

In this case, TI's NexFET™ CSD16404Q5A, with an RDS(ON) = 5.6mΩ and QSW = 3.2nC (Ratio = 1.78) would be the best potential choice.

MULTIPLE POINT OPTIMIZATION

Another application of the ratio of sums for the J/K method is optimizing for multiple points. This works best in systems with known load duty cycles where each operating point can be weighted by the operational time at that point. As long as both J and K of each operational point are equally weighted, the process works and selects the MOSFET with the lowest total energy loss at those operational duty cycles.

For example, a radar system will spend 2ms transmitting followed by 10ms receiving reflections. The designer determines the need to deliver 10A of current during a transmit period, but only 4A during a receive period. By selecting a MOSFET with:

Designer selects a MOSFET that offers the lowest total power loss over the entire 12ms cycle, thus optimizing the design for overall efficiency.

PARALLELING MULTIPLE MOSFETS

Sometimes multiple MOSFETs in parallel are required. While placing two identical MOSFETs in parallel does little to change their RDS(ON) x Qsw product, much like paralleling multiple MOSFET cells within a discrete device, it significantly alters the RDS(ON) to Qsw ratio. Each MOSFET in parallel reduces the resistance and increases the gate charge. Paralleled MOSFETs have 1/N2 the RDS(ON)/ Qsw ratio of individual MOSFETs. To apply the J/K method here, choose a MOSFET such that:

Where N = number of MOSFETs in parallel.

MOSFET selection is simplified by focusing on losses caused by the MOSFET. MOSFET selection for maximum efficiency is a balance between increasing MOSFET size to reduce RDSON, and reducing size to reduce switching charge. You can now summarize an application operating point with a simple ratio of switching and conduction losses. The J/K method allows you to quickly and efficiently narrow MOSFET selection from a vast array of available devices to a limited number of suitable MOSFETs by comparing available devices to this simple ratio of switching and conduction losses.

References

TPS40192 datasheet

CSD16412Q5A, datasheet

CSD16407Q5. datasheet

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