PCPM | Peak Current-Mode DC-DC Converter Stability Analysis

Jun 1, 2010 12:00 PM
TIMOTHY HEGARTY Principal Engineer, Infrastructure Power Division National Semiconductor, Tucson, AZ

Popularity and perceived advantages of current-mode control (CMC) have made it de rigueur as a loop control architecture with many power management IC manufacturers and power supply vendors. Also known as multi-loop control, an external voltage loop and a wide-bandwidth inner current loop are standard. Peak, valley, average, hysteretic, constant on-/off-time, and emulated current-mode techniques are realizable. Top of the agenda is usually peak current-mode control (PCMC) with slope compensation. Notable advantages of PCMC include automatic input line feed-forward, inherent cycle-by-cycle overload protection, and current sharing capability in multi-phase converters. Acute shortcomings are current loop noise sensitivity and switch minimum on-time limitations, particularly in high step-down ratio, non-isolated converter applications. The emulated (sample-and-hold) architecture^[1,4] largely alleviates these shortcomings, however, while preserving the benefits of PCMC.

The converter in Figure 1 represents a single-phase buck topology operating in continuous conduction mode (CCM), and whose duty cycle, D, is determined by recourse to the principles of PCMC. Note that the parasitic resistances of the filter inductor and output capacitor are denoted explicitly. Other buck-derived power stage topologies - including isolated forward, full-bridge, voltage-fed push-pull - could also be inserted here, while retaining a similar loop configuration (feedback isolation excepted).

In a peak current-mode architecture, the state of the inductor current is naturally sampled by the PWM comparator. The outer voltage loop employs a type-II voltage compensation circuit and a conventional operational transconductance error amplifier (EA) is shown with its inverting input, labeled the feedback (FB) node, connected to feedback resistors R_fb1 and R_fb2. A compensated error signal appears at the EA output, labeled COMP, the outer voltage loop thus providing the reference command for the inner current loop. COMP effectively represents the programmed inductor current level. The current loop converts the inductor into a quasi-ideal voltage-controlled current source, effectively removing the inductor from the outer loop dynamics, at least at DC and low frequencies.

The current sensing location in Figure 1 is shown schematically after the inductor. The implementation could be a discrete shunt resistor, or lossless using inductor DCR current sensing^[5] or measuring MOSFET on-state resistance^[2]. Alternatively, a current sense transformer can be exploited, but only if the current sense location is such that the current waveform is zero for part of the switching period to allow transformer reset, e.g. in series with the high-side FET. In any event, the equivalent linear amplifying multiple is given by:

Where:

G_i = Current sense amplifier gain (if used)

R_s = Current sensor gain given by one of:

A perfect current-mode converter relies only on the dc or average value of inductor current. In practice, a peak-to-average inductor current error exists in a PCMC implementation and this error can manifest itself as a sub-harmonic oscillation of the current loop in the time domain at duty cycles above 50%. Slope compensation is the well-known technique of adding a ramp to the sensed inductor current to obviate the risk of this sub-harmonic oscillation. Figure 2 illustrates how a turn-on command is activated when the clock edge sets the PWM latch. A turn-off command is imposed when the sensed inductor current peak plus slope compensation ramp reaches the COMP level and the PWM comparator resets the latch. This is known as trailing edge modulation. Se, earmarked in Figure 2, is the external slope compensation ramp slope and S_n and S_f are the on-time and off-time slopes of the sensed current signal, respectively. D' = 1-D is the duty cycle complement.

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