Innovative Packaging Shrinks 600 mA and 6 A Power Supplies

Jan 1, 2011 12:00 PM
Sam Davis Editor-in-Chief

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ONE OF TI'S introductions is the 6 A TPS84620 that uses innovative lead frame packaging to achieve 800 W/in.³ power density with up to 95 % efficiency. Thermal impedance is 13°C/W junction-to-ambient, which is a 30% improvement over previous generations. The device delivers its full 6 A rated output over a -40°C to 85°C ambient temperature without external airflow.

As shown in Fig. 1, the TPS84620 is a synchronous buck converter integrating an inductor and passive components. It requires only three external components: input and output capacitors and a resistor (RSET) that sets the output voltage. The entire circuit fits into a low profile, 9×15×2.8 mm BQFN package with less than a 200 mm² footprint.

The TPS84620 operates from a 4.5V to 14.5V input. Output adjustment range is from 1.2V to 5.5V using the external RSET resistor. An optional split power rail allows inputs down to 1.7V. Its adjustable switching frequency range is 480 kHz to 780 kHz, synchronizable to an external clock.

Various applications are possible for the converter by using the VIN and PVIN pins together or separately. VIN supplies the internal control circuits. PVIN provides the input voltage to the power converter system. With both pins tied together, the input voltage can range from 4.5V to 14.5V. Using the VIN separately from PVIN, the VIN pin must be between 4.5V and 14.5V, and the PVIN pin can range from 1.7V to 14.5V.

An internal UVLO (undervoltage lockout) circuit disables the device if VIN falls below its 4.5V (max) threshold and 150 mV (typical) hysteresis. If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, you can program the UVLO pin for the new value.

During power up of the converter, internal soft-start circuitry limits in-rush current drawn from the input source. The converter's soft-start circuitry introduces a short time delay from the point that it recognizes a valid input voltage.

The PWRGD pin is an open drain output. Once the voltage on VSENSE+ is between 94% and 106% of the set voltage, it releases the PWRGD pin pull-down and the pin floats. In operation, use a PWRGD pull-up resistor of 10 kΩ to 100 kΩ connected to 5.5 V or less.

VSENSE+ must be connected to VOUT at the load, or at the device pins. This improves load regulation by allowing the device to compensate for any I×R voltage drop between its output pins and the load. The high output current flowing through the pin and copper trace resistance can cause and I×R drop that should be limited to 300 mV (max.).

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