Generate Auxiliary Voltages at Low Cost

Jan 1, 2008 12:00 PM
By John Betten, Application Engineer, Texas Instruments, Dallas

Excellent cross regulation and high efficiency can be achieved with this technique. The drawback is that access to the low-side FET gate-drive signal is required to drive the synchronous coupled-inductor FET. This eliminates the use of synchronous buck controllers that have integrated top and bottom FETs. The circuit in Fig. 5 bypasses this limitation by using a p-channel FET.

The Fig. 5 circuit operates identically to that of Fig. 4, except the gate drive to the p-channel FET is driven out-of-phase by the switch node, rather than the bottom FET gate drive. Care must be taken when a p-channel FET is used in this configuration that the gate-source voltage available is adequate to ensure full enhancement in steady-state operation.

The maximum turn-on V_GS in Fig. 5 is equal to V_OUT2, since the FET switches on when the switch node pulls to ground. This places a limit on the maximum output voltage that V_OUT2 can be, as many p-channel FETs have maximum V_GS ratings of only 8 V or 12 V. A maximum reverse V_GS equal to the input voltage (V_IN) is applied when the switch node pulls to the input voltage and the output voltage is zero, which occurs at startup.

Fig. 6 shows a synchronous version of the circuit shown in Fig. 1c, using an n-channel FET for the auxiliary output. The gate-drive voltage for Q3 is derived from the gate-drive voltage of bottom FET Q2, allowing both FETs to switch in phase with each other. Capacitor C1 ac-couples this switching signal, but blocks its dc average level. Diode D1 conducts only during the negative swing of the Q2 drive voltage, clamping Q3's gate voltage to 0.7 V below the source and turning it off.

During the positive swing of the Q2 drive voltage, V_GS for Q3 is equal to the Q2 gate-drive voltage, less a diode drop, turning it on. The use of 2.5-V_GS threshold parts may be necessary if the gate-drive voltage is 4.5 V to 5 V. Without D1, the positive V_GS would vary with duty cycle, creating a situation where FET Q3 may not have enough drive voltage to turn on properly.

Charge Pumps

The circuit in Fig. 7 is a boost converter with a charge pump that generates a negative auxiliary output voltage. The charge-pump circuit is composed of C2, C4, D3 and D4. When the FET turns off in a boost converter, the stored energy in the inductor is transferred to the output capacitor and load through diodes D1 and D2. At the same time, D4 conducts and C2 is charged to the output voltage plus a diode drop.

When the FET turns on again, the voltage on C2 pulls the charge-pump output negative through D3. The two diodes in the boost converter (D1 and D2) are necessary to cancel the forward-voltage drops of the two diodes in the charge pump (D3 and D4). Excellent voltage regulation is achieved for light loads on the (negative) charge-pump output.

The circuit in Fig. 8 is a charge pump that boosts the V_OUT2 output voltage to the input voltage plus the V_OUT1 output voltage. When the internal synchronous FET of the TPS62007 controller switches to ground, it charges C3 to the V_OUT1 output voltage, less one diode drop. Then the internal control FET turns on, pulling U1 pin 9 to V_IN. This action forces the charge stored in C3 into output-capacitor C5.

As with most charge pumps, there are two diode drop reductions in the output voltage in Fig . 8. This circuit is useful in applications where the input voltage is well regulated or where the auxiliary output can feed the input to a linear regulator for a lower output voltage.

Fig. 9 is a variation of Fig. 8, but provides a negative output voltage at V_OUT2. The output voltage of the charge pump is equal to the inverted input voltage, less two diode drops.

The circuit in Fig. 10 is a multiple-output flyback using a stacked-winding transformer. Regulation is achieved by feedback from output V_OUT2. The addition of diode D1 and C9 creates a negative-output V_OUT4 that is equal in magnitude to V_OUT2.

Energy is transferred to all outputs only during the off time of FET Q1. During this interval, a negative voltage equal to V_OUT2 is imposed across the primary winding, due to a 1:1 turns ratio between the primary winding and the V_OUT2 stacked winding. With a negative V_OUT2 clamped across the primary winding, diode D1 charges capacitor C9, resulting in a voltage on output V_OUT4 that is closely matched to V_OUT2.