SPICE3 Enables Accurate Modeling of Complex ICs

Nov 1, 2006 12:00 PM
By Larry Meares, President and Chief of Custom Modeling, and Tim Ghazaleh, Marketing Director, Intus

One-Cycle Control PFC IC

The gain of the integrator within the IR1150 IC (click to view Fig. 5) is an important factor in making the load appear resistive as the input voltage varies. Integrator gain is not discussed in the data sheet or application note. A simulation was performed to find out how the gain varies with frequency to maintain the proper power-factor-correction (PFC) behavior. Two voltages, 150 V and 75 V, were used to find out the required gain. The relationships are shown in the table.

The circuit used to test the PFC stage of the IR1150 is essentially the one described in its application note, except that a 2-µH boost inductor was selected to make some of the earlier runs have lower ripple current. In the simulation, a 1.5-µH inductor in parallel with a 50-Ω resistor was used to simulate a ferrite bead in series with the output. Not only does the EMI signature improve but so does simulator convergence. The EMI filter might need revising, using two sections to meet the conducted emissions requirement. Alternatively, the frequency could be modulated by connecting a resistor between the rectified ac and the FREQ pin. Properly adjusting the steady-state COMP pin voltage enables shorter simulation time.

PWM Controller IC

In simulations of UCC2891 current-mode active-clamp PWM controller IC (click to view Fig. 6), the internal oscillator is modeled separately. Ideal current pulses are used to simulate the gate-drive signals, and are thus reflected back to V_DD. However, this idealization still provides correct peak current, rise/fall times and drive impedance.

In the UCC2891 test circuit (click for PDF), second-order effects were estimated for the power transformer, filter inductor, magnetic di/dt coupling and filter capacitors in order to see parasitic ringing. This ringing may need to be filtered to comply with EMI specifications. Additionally, the measurement of this parameter in the test circuit is affected by scope bandwidth.

The causes of high-frequency output ripple include: the combination of the ceramic capacitor and electrolytic capacitor lead-inductance, and the filter-inductor parallel capacitance; magnetic coupling between the switching loop and filter loop; and electrostatic coupling by the transformer parasitic capacitance.

Input ground and output ground are assumed connected together externally. Your lab power supplies will do this via their own EMI filters and the application will probably connect them via the safety ground (as simulated by L2 in the SPICE test circuit). Moreover, there will be some parasitic capacitance connecting them on the printed wiring board (simulated by C3 in the SPICE test circuit). The noise current in the parasitic capacitance has high amplitude and is very broad in bandwidth, hence the need for better EMI filtering.

The TLV431A Zener model that was used for the simulation requires the SPICE RSHUNT option to converge. Time step is under the control of a special VSECTOL convergence option in the simulator. The initial operating point is automatically calculated using another special convergence option, ICSTEP.

For successful modeling of today's complex ICs, special convergence options must be built into a high-end SPICE3 simulator's kernel. Other aids include general feedback theorem (GFT) injection models for preserving closed-loop dc bias while taking open-loop measurements, ultrafast average modeling technology and modeling savvy. As with any design-automation tool, simulation will ultimately achieve a more production-ready system by tackling worst-case design and test scenarios before going to pc-board fabrication.

Information on GFT injection models are available at http://intusoft.com/gft.htm.

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