DSCs Ease Migration to Digital Loop Control

Nov 1, 2006 12:00 PM
By Bryan Kris, Staff Architect, Architecture & Applications, Digital Signal Controller Division, Mic

The appropriate PWM operating frequency must be determined, considering that a higher frequency PWM enables the use of smaller inductors and capacitors, but at the cost of additional switching losses.

A key factor to consider when selecting a DSC for this application is to ensure that the onboard PWM module provides adequate resolution for the SMPS design. A resolution that is not high enough will cause the control system to dither the PWM outputs to achieve the desired output, which can create problems with ripple currents and cause the control to enter an unfavorable mode of operation called limit cycling.

Limit cycling is the dithering that the control loop and PWM module cause when the PWM module does not provide sufficient resolution. The control loop will dither the PWM duty cycle, frequency or phase (depending upon the mode of operation) to obtain the desired output voltage or current. This PWM-dithering process occurs at a subcycle basis, where the PWM signal is either greater or less than the needed value. Over a long period of time, the control loop will meet the desired end state, but at a cost that includes increased current and voltage ripple.

How significant is this need for high PWM resolution? Most DSCs available on the market offer PWM counters that operate in a range from 40 MHz to 150 MHz, yielding PWM resolutions of 6 ns to 25 ns. A PWM with at least 1-ns duty-cycle resolution is needed for digital loop control.

At the operating PWM frequency, the PWM resolution should be comparable to or better than the voltage/current feedback devices' resolution. For example, if the ADC or comparator DAC has 10-bit resolution and the PWM is operating at 1 MHz, then the PWM resolution should also be 10 bits. With a PWM frequency of 1 MHz (1-µsec period), a PWM generator with 1-ns resolution is capable of subdividing the PWM signal into 1024 pieces, yielding 10-bit resolution.

The ADC onboard a DSC used for digital loop control provides the system with status (feedback) to the control loop. Most ADCs on the market are designed with the assumption that their values are collected and processed in a “group.” For example, ADCs used in audio processing and industrial-control systems typically function in this manner. In these cases, group sampling causes the processor workload to peak in groups, which increases control-loop latency.

Often in SMPS circuits, the analog signal to be sampled and converted does not exist, or may not be significant, at all times. The signal may only be important at specific points in the PWM cycle. Therefore, ADC modules that sample in groups may miss the desired data due to imprecise sample timing.

As ADCs cannot continuously monitor signals, samples can only be processed up to the ADC's mega-samples-per-second (MSPS) rating. Some DSCs feature analog comparators that free up the processor and ADC to perform other valuable tasks.

For example, the reference DACs and analog comparators on some DSCs can achieve latencies from current measurement to PWM update of approximately 25 ns. This response time is much faster when compared to other DSCs that rely on “polling” techniques with the ADC and processor to modify the PWM outputs in response to changing conditions. This “nonpolling” method is how the more power-conversion-centric DSCs implement the cycle-by-cycle current-limiting function required for current-mode control.

Implementing current-sensing circuitry in SMPSs is difficult because high currents, fast voltage rise times and pc-board trace inductance often lead to transients in the current-sense circuitry. These transients often occur during the start of the PWM cycle. With the leading-edge blanking (LEB) function, designers can ignore false positives on the fault inputs to the PWM module for a short period of time at the start of a PWM cycle. The inclusion of more fault inputs and modes of operation, combined with LEB support, offers distinct benefits for SMPS designs.

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