Control Method Solves Low Duty-Cycle Dilemmas

Sep 1, 2006 12:00 PM
By George Hariman, Circuit Design Engineer, and Chris Richardson, Applications Engineer, National Se

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Modern buck switching-regulator circuits need to provide lower and lower output voltages to power leading-edge digital logic ICs such as digital signal processors, field-programmable gate arrays and microcontrollers/microprocessors. Supply voltages in the range of 1 V and below are starting to become ubiquitous,^[1] yet intermediate bus voltages still stay at their traditional level. One of the “silver box” power-supply outputs is an unregulated 12-V line, which is considered a standard intermediate voltage bus level.

Furthermore, switching frequency requirements have steadily increased with the demand for smaller magnetic components. While it was common to find buck switching regulators operating at around 200 kHz to 300 kHz a few years ago, it is now common to see buck switching regulators operating at 500 kHz, 750 kHz and even beyond 1 MHz.

All of these trends translate to the requirement that the buck switching regulator be able to provide extremely short duty cycles, or equivalently, extremely narrow high-side FET on-time pulses. However, traditional peak-current-mode control falls short in being able to provide very low high-side on-time. Meanwhile, valley-current-mode control, which regulates at very low duty cycles, introduces other problems related to subharmonic instability and line regulation. But a new approach known as emulated-peak-current-mode control overcomes the limitations of peak-current-mode and valley-current-mode control.

Peak-Current-Mode Control

Most fixed-frequency, current-mode control buck switching regulators employ trailing-edge modulated peak-current-mode control. That's because trailing-edge peak-current-mode control exhibits a control-to-output — sometimes known as the power stage — that has minimal phase shift, popularly known as having a “one-pole roll-off characteristic.”^[2] This makes compensation of the control loop easier than voltage-mode control (Fig. 1).

When low duty-cycle operations are demanded, however, trailing-edge peak-current-mode control exhibits a disadvantage. Inductor current information in trailing-edge peak-current-mode control is sensed across the high-side FET, or a resistor in series with the high-side FET. During turn-on of the high-side FET, the switch node will exhibit a lot of ringing due to parasitics on that node. Therefore, peak-current-mode switching regulators usually employ blanking time before sensing the inductor current. Normal values for blanking time are around 200 ns to 300 ns^[3] (Fig. 2).

Because of this blanking time requirement, trailing-edge peak-current-mode switching regulators will not be able to regulate to very low high-side FET on-time requirements. In other words, traditional trailing-edge peak-current-mode switching regulators will not be able to correctly regulate a 1-V output voltage from a 12-V input voltage at 500 kHz. This set of conditions requires a duty cycle of one-twelfth, which translates to a high-side FET on-time of 167 ns. This on-time is shorter than the 200-ns blanking time.

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