Exploit Controller Features to Optimize Power Designs

Jun 25, 2008 3:07 PM
By Ricardo Capetillo, Applications Engineer, Linear and Low Voltage, National Semiconductor, Santa Clara, Calif.

Feedback Voltage Accuracy

The demand for faster processing speeds, conservation of battery life and thermal considerations have driven digital processors to decrease their operating voltage. To maintain predictable logic-level states, it is particularly significant for the SMPS to have tight feedback-voltage accuracy across an extended die temperature range of -40°C to 125 °C. Capacitance reduction is also feasible when using a ±1% feedback accuracy device over ±2% devices.

According to field-programmable gate-array power requirements, an output-voltage response to a line or load transient must not exceed ±5% of the nominal 1.2-V supply voltage. With a ± 2% dc accuracy device, this leaves the output-voltage supply with only ±36 mV of allowable voltage swing. With a device with a dc accuracy of ±1%, the allowable output-voltage budget is now wider at ±48 mV.

In a typical example as shown in Fig. 4 and Fig. 5, based on a 350-mA to 6-A load transient response, equal loop-gain bandwidth and phase margin, a 1% device accuracy over a 2% device realizes a 50% reduction in output capacitance. A tighter feedback-voltage accuracy specification can translate to lower-value capacitors, saving cost and total solution size.

Tracking and Precision-Enable Features

Modern mixed-signal systems require multiple voltage-supply rails, which power the processor core, I/O, and other analog and digital circuits. Each voltage rail calls for a different voltage and load rating. The startup timing of each voltage rail, in reference to each other, is a critical requirement. Keeping the voltage differential minimized during powerup and/or keeping them sequenced will prevent latchup, bus contention and undesirable transistor logic states.

The precision-enable feature provides sequential timing necessary for proper startup. A second method of sequencing is the tracking feature. Tracking gives control to the master power supply over the slave’s startup rise time.

Two common tracking methods are: ratio metric, where the supply voltages reach their regulation point at the same time, and simultaneous startup, where the supply voltages increase with equal slew rates, as shown in Fig. 6 and Fig. 7, respectively. Tracking and precision-enable allows several voltage rails to reach their nominal voltages within a specified target time.

Prebiased Startup Feature

In reference to the SMPS, prebiased startup is defined as starting up into a biased output rail. Common output-voltage prebiased situations include redundant power supplies, multiphase voltage-regulators modules, or cycling of the SMPS under no-load or light-load conditions.

Discharging the output capacitor may lead to conditions such as the voltage and current of one rail sneaking into the output of another rail through a parasitic p-n junction, which potentially may cause the leakage component to fail. Other loads may trigger the output power-good flag, output undervoltage protection and/or the output current protection of the voltage regulator IC.

In many situations, accidentally discharging a prebiased load on the output rail of a SMPS is not acceptable. Only regulators with synchronous rectification have the ability to discharge the output capacitor in a prebiased condition through the low-side MOSFET. Synchronous SMPS equipped with soft-start prebiased circuitry are able to sustain a charged output capacitor during the power-up period. This feature prevents the inadvertent discharge of the output rail during a prebias startup.

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