Dual-Edge PWM Improves Multiphase Regulators

Jul 1, 2007 12:00 PM
By Weihong Qiu, Principal Applications Engineer of Computing Products, and Greg Miller, Vice Preside

Limitations of Conventional PWM

Fig. 1 shows the output stage of a typical 4-phase voltage regulator. Assuming that the high-voltage spike caused by the bulk-capacitor equivalent series inductance (ESL) is absorbed by the high-frequency ceramic capacitors, the capacitor equivalent series resistance (ESR) and the inductor current slew rate become the main factors that impact the transient performance. When the load step is applied to the voltage regulator, the output voltage will drop immediately and the initial voltage drop depends on the ESR of the output capacitor. AVP control will regulate the output voltage to the new value based on the output current.

During the settling time, the output capacitor is discharged to provide some portions of the load current, while the inductor current increases in response to the larger load current. When the inductor current slew rate matches that of the discharging current from the output capacitor, the output voltage waveform can approach an ideal square wave, if desired. Thus, with an increase to the total inductor current slew rate, the current demand on the output capacitors will be reduced and less output capacitance will be required.

There are two parameters that determine the time for the total inductor current to ramp up to the load current: the delay time of the PWM pulses and the slew rate of the total inductor current. To reduce the delay of the PWM pulses, the PWM modulator should respond to the error amplifier voltage change as soon as possible. For a given system, the phase inductor current slew rate is fixed, set by the input voltage, output voltage and inductance.

To obtain a faster total inductor current slew rate, more than one phase can be turned on simultaneously. This requires the PWM modulator to allow phase overlap and turn on additional phases proportionally to the step load. Based on these observations, the PWM modulator plays an important role in achieving fast transient response.

Fig. 2 shows a typical voltage regulator with a conventional trailing-edge PWM scheme. In trailing-edge modulation, the error amplifier output (V_COMP) is compared to a ramp signal to generate the PWM signal. To reduce the noise impact and avoid multiple PWM pulses in one switching cycle, an R-S flip-flop is typically used. However, the R-S flip-flop brings an additional response delay to the system.

The worst-case delay would be in the trailing-edge modulation scheme, when a PWM pulse is turned on by the clock and terminated by the intersection of the ramp signal and VCOMP. Therefore, the modulator cannot respond to a change after PWM goes low until next cycle.

As shown in Fig. 2, V_COMP may jump above the ramp signal at T3; however, the PWM signal stays low until the next clock pulse at T4, resulting in a turn-on delay (T_DELAY). The turn-on delay can cause extra voltage drop in the event of load step. The trailing-edge modulation scheme can respond quickly to any change when the PWM pulse is high, so it can turn off the PWM pulse without delay. Therefore, the trailing-edge modulation scheme has an excellent turn-off response but a poor turn-on one.

Want to use this article? Click here for options!
© 2007 Penton Media, Inc.