Dual-Edge PWM Improves Multiphase Regulators

Jul 1, 2007 12:00 PM
By Weihong Qiu, Principal Applications Engineer of Computing Products, and Greg Miller, Vice Preside

Click here for the enhanced PDF version of this article including diagrams and/or equations.

Transient response is a key performance parameter for the multiphase voltage regulator, especially in microprocessor applications. Conventional pulse-width modulation (PWM) schemes have delay times that can increase the demand on the output capacitors, forcing designs to employ more capacitors for acceptable performance.

A new PWM scheme called active pulse positioning (APP) achieves very fast transient response by dramatically reducing the modulator delay time. This modulation scheme adopts two separate ramp signals to control both the leading edge and trailing edge of the PWM pulse. Controller ICs that implement APP modulation can respond to transient events immediately and require much less output capacitance than other modulators.

Regulating Dynamic Loads

With fast transient response, less output capacitance is needed to meet the design specifications for the regulator. For most applications, the output voltage will drop to its minimum value in several switching cycles after the step load is applied and then settle to its final value slowly. For these applications, increasing the closed-loop bandwidth is important for fast transient response.

This situation is compounded for multiphase voltage regulators for microprocessor core power applications. The current drawn by modern microprocessors is highly dynamic with a wide-varying transient duration and repetition rate. The typical step-load current can be as high as 100 A with a slew rate up to 1000 A/µs. To address this demand, the voltage regulator needs its output voltage to settle rapidly after the transient event in order to be ready for the next transient event.

Adaptive voltage positioning (AVP) control, also referred to as droop control or load-line control, is a popular scheme used to power today's microprocessors. With this control, the output voltage will be reduced in proportion to the load current; the output voltage at heavy load is lower than that at light load, resulting in more cost-effective transient-load regulation. The output voltage after the step load does not need to return to its original value, resulting in much shorter settling time.

The typical response and settling time for the voltage regulator with AVP control is only a few microseconds in typical microprocessor core regulators. With a typical 300-kHz switching frequency, this means the transient event can occur and the regulator must respond completely within one switching cycle. Therefore, any delay in the system will have significant impact on the transient response, and the conventional loop bandwidth concept is not adequate for analyzing the regulator performance. Instead, it is necessary to investigate and reduce the delays in the entire system to improve the transient performance.

Want to use this article? Click here for options!
© 2007 Penton Media, Inc.