The design of a modern motor control system is complex, requiring an in-depth understanding of the associated technologies. The designer needs a working knowledge of control system algorithms, microcontrollers and digital signal processors (DSPs), sensor signal measurement and A/D converters, high voltage interface and gate drivers, and the output inverter power stage. Advanced power intelligence and robust protection of the power stage and motor require an expanding knowledge base of motor drive systems. Traditional methodologies don't efficiently partition the design tasks into well-defined architectural elements with standardized interface protocols. This can result in complex and customized designs, high initial product costs, and high lifetime ownership costs.

To provide a flexible, versatile, and performance-oriented power management architecture, designers created the Accelerator^™. This new chipset architecture accepts micro- or DSP controller inputs and drives a 3-phase inverter power stage. It enables more freedom of microprocessor choice — which is not necessarily motion control specific. Several guiding principles behind the design are intelligent partitioning, standardized interface protocol, and performance enhancement of the power management functions. The most fundamental concept is treating the inverter as an “intelligent power management peripheral” for the microcontroller or DSP.

It is now possible to write control system software at a higher hierarchical level — without the need to program at the bit level for motor control power management functions, such as voltage pulse width modulation (PWM), dead time generation/compensation, diagnostic and protection, and the voltage and current measurement interface. The chipset can integrate the high-voltage analog and power circuits that turn algorithms into power transfer commands, along with other power management functions. A mixed signal of 0.5 μm CMOS, and a high voltage BCDMOS with a rating from 600V to 1200V make up the chipset. You can apply the chipset to a variety of applications driving ac or brushless dc motors for: industrial ac drives, industrial servo drives, appliance drives (air-conditioner, washing machine, refrigerator compressor), robotics, electronic power steering (12V, 42V), integrated starter alternator (42V), and high-reliability drives for aviation and space.

As you can see in Fig. 1, on page 20, the chipset's four functional elements include high-speed serial interface, PWM waveform and dead time generator with fault diagnostics, motor current sensing and feedback processing, and IGBT Gate drive with ground fault protection.

These elements integrate into four advanced silicon devices, using high voltage monolithic integration. The Photo, left, shows an example of the integration of the Accelerator^™ chipset driving an EconoPIM2 IGBT power module (600V/30A). Its microprocessor input employs the SPI high-speed serial communication protocol.

This new architecture expands power conversion design flexibility, while substantially increasing power intelligence capability. PWM waveform generation, dead time, and fault diagnostic functions are integrated into a single monolithic chip, when compared with the fragmented IGBT protection and motor phase current feedback function of a traditional intelligent power module (IPM). The final integration and mechanical form of this new chipset-based IPM can be taken as an essential part of the power management design, or used with the EconoPIM2 IGBT output module.

Designers configured this motor control chipset as an intelligent power management peripheral for microcontrollers or DSPs. A unique power management peripheral (PMP) IC is the key element enabling the independent enhancement of this power management function. Some PMP functions are implemented in the motion control microcontroller or DSP, but these are limited in terms of integration and power intelligence enhancement. In contrast, the new power management peripheral chipset integrates several functions in a minimum number of chips. Fig. 2 shows the block diagram of the power management peripheral.

The PWM waveform generator can accommodate any of today's advanced PWM schemes, including space vector modulation and third harmonic injected modulation. You can attain the maximum resolution at 33 ns with a 12-bit resolution for voltage command and carrier frequency. Independent override bit control enables a different commutation scheme to achieve six-step plus partial PWM excitation — apart from sinusoidal commutation such as trapezoidal commutation. You can also implement eight-bit dead time insertion logic with a 33 ns resolution counter. Voltage command, PWM carrier frequency, and dead time are double buffered and updated synchronously with the end of each PWM carrier frequency period. Therefore, the CPU can allow a coherent update of these values during any moment of execution time.

The PWM unit interfaces with any gate drive component, including any high voltage IC (HVIC) and opto-coupled devices. It also contains shutdown logic in conjunction with the external fault signal interface.

Implementing a current-feedback processing unit is possible by a maximum 132 MHz fast counting block that interfaces directly with high voltage, monolithic current sensing ICs (IR2171/IR2172). The resulting motor current feedback resolution is 12 bits and is updated synchronously with the CPU's current control loop execution.

The unit also contains a fast multiply/divide block (it takes less than 400 ns to achieve 12 bit multiply/divide computation) to eliminate current measurement temperature drift. You can do this by simultaneously measuring the IR2171 output carrier frequency and the varying duty period relative to the measured motor current. This is based on the unidirectional/linear variation between the carrier frequency and duty period. Fig. 3 on page 24, illustrates a detailed block diagram of the current measurement unit. This current feedback-processing unit also includes offset cancellation logic.

Fault diagnostics generate a snapshot of data containing the last four states of current feedback data, voltage vector, and the discrete fault status I/O pins in the event of drive fault condition. This enables the user to quickly diagnose a drive system fault, which minimizes the downtime of the entire coordinated system.

The power management peripheral IC contains a popular serial communication protocol interface — SPI interface, to communicate with any microprocessor or DSPs as long as it contains the communication interface peripheral. The PMP device is configured to be slave mode, allowing the additional peripheral devices to share the same SPI bus in the system, such as E²PROM and analog digital converters (ADCs). This bus configuration capability also enables easy integration of multi-axis drive application where one host microprocessor, or DSP, serves as a master while multiple PMP-driven power units are configured as slave. This requires four serial signals, namely SCK (serial clock), MISO (Master Input Slave Output), MOSI (Master Output Slave Input), and CS (Chip Select). Communication throughput is carefully designed to meet today's high bandwidth data traffic between the host and the PMPs. The data transfer rate can sustain up to 6 mega bit/sec enabling, 9 ms of communication time to update the phase voltage command and two sets of current feedback data. If the carrier frequency and the CPU update rate is 10 kHz, then the communication time becomes less than 10% of CPU loading. You can devote the remaining time for calculation required to perform the field orientation or the closed current control algorithm execution.

The 3-phase inverter power stage usually consists of three high-side and three low-side IGBTs or MOSFETs, operating from a high voltage dc bus. The bus voltage varies depending on the application, ranging from 12V for automotive to 600V for 230Vac and 1200V for 460Vac industrial drives. Previous methods use discrete opto-couplers to provide the high-voltage gate drive to the IGBTs or MOSFETs. High-voltage IC technology enables the integration of a 3-phase gate driver in a single chip such as the industry standard IR213× (600V) and IR223× (1200V) product families. The first series of the motor control chipset integrates the 600V IR2137 or 1200V IR2237 in the gate driver function, including IGBT de-saturation protection and synchronized soft shutdown. Robust protection against short circuit conditions such as line-to-line short, ground fault and shoot-through results in controlled di/dt and no voltage spike across the IGBT during short circuit turn off, as shown in Fig. 4.

Traditionally, Hall effect sensors, or more recently linear opto-coupling devices implemented the current sensing function. This hybrid construction severely limits power integration.

Recently developed monolithic high voltage integration ICs can measure the motor current accurately in 230V/460V ac drive inverter applications. A practical application example has begun with these HVIC current-sensing ICs, such as the IR2171.

Bandwidth performance is also an important factor for closed loop current control applications. The Bode plot in Fig. 5 shows the IR2171 and the power management peripheral test data. The test data illustrates how the device sustains 17 kHz at -3 dB, which also practically enables the closed current control loop to yield 1 kHz system bandwidth.

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