Power Limits Make Hot Swapping More Robust

Jan 1, 2008 12:00 PM
By Neil Gutierrez, Design Engineer, High-Voltage Power Management Group, National Semiconductor, Pho

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Hot swapping, the act of inserting and removing circuit boards into an active backplane has been used in telecom servers, USB interfaces, firewire interfaces and CompactPCI applications.^[1] By keeping the system backplane voltage live, faulty boards can be removed and replaced with new boards, but still keep the system live for other boards in the system. In general, an external FET is used with a hot-swap controller to control the inrush currents. But not all hot-swap controllers are created equal.

Using some hot-swap controllers to control inrush currents can make hot swapping into a live backplane unreliable. The capacitors on the circuit boards provide a low-impedance path for the supply, causing large inrush currents. The inrush currents can cause damage to board capacitors, trace lines and connectors. The system voltage can drop below the system-reset threshold due to the inrush currents and cause other boards connected to the backplane to reset.

This scenario can be reliably averted by picking a controller that combines both programmable power and current limiting. In turn, this allows you to maintain a margin of safety to the safe-operating-area (SOA) boundary for reliable protection without the need to oversize the external FET.

Hot-swap controllers are designed to limit the inrush current by controlling an external FET. The controllers also limit the current during fault conditions when the output shorts out to ground or there are large load transients.

One can assume that picking a FET that can withstand the dc current load and maximum input voltage would be sufficient. However, controllers that only have the ability to control the current cannot guarantee the FET will stay within the SOA under all operating conditions.

There are controllers that can provide both power-limit and current-limit control. One such example is National Semiconductor's LM5069 IC (Fig. 1). The inrush current is sensed across the sensing resistor (R_SENSE). The controller will only allow a maximum voltage across R_SENSE. If the voltage increases beyond the maximum voltage, the controller will modulate the gate voltage to keep the current at a maximum level, the current-limit mode.

The maximum power across the FET is programmed through the PWR pin. If at any time the power across the FET (V_DS × I_LIMIT) is greater than the programmed power limit, then the I_LIMIT is reduced such that the FET power is equal to the programmed power limit, the power-limit mode.

The maximum current (I_LIMIT) will be maintained for a limited amount of time.

The maximum time allowed for the current limit is programmed through the timer pin by the fault-detection current, fault threshold and external capacitor. Once the timer reaches the fault threshold, the controller shuts off the gate and the output is disconnected from the system input voltage.

System undervoltage and overvoltage are detected through a resistor divider on the undervoltage lockout (UVLO) and overvoltage lockout (OVLO) pins, respectively. The part verifies that the input voltage is within a specific range, above the undervoltage threshold and below the overvoltage threshold. If the input voltage is out of range, then the gate shuts off. The power good pin (P_GD) is an open drain output. When the output (V_OUT) reaches the input (V_IN) within 1.25 V, the open drain pull-down device is disabled and P_GD is pulled up through the pull-up resistor to the V_OUT rail. The P_GD output can be used to flag downstream circuitry to indicate that the V_OUT voltage is “good.”

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