Designing with DrMOS, Part II: Application Guidelines

Mar 1, 2011 12:00 PM
Sanjay Havanur, Principal Applications Engineer Alpha and Omega Semiconductor

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Traditionally in synchronous buck designs, the PWM controller and its driver have been a single unit, for cost and space considerations. The downside was that the PWM IC with the most desired features did not always come with the most powerful driver. Nor was it possible to closely match that one driver to different power devices. DrMOS offers a logical solution to the problem, putting all the unintelligent components of the buck converter in one package. Co-packaging the driver with two MOSFETs has its challenges but gives a great deal of flexibility to designers, who can derive a logic level PWM signal from anywhere in their system.

Since the PWM signal is provided from an external controller or a digital processor, extra care must be taken during start up. DrMOS modules must be powered up and enabled before the PWM input is applied. It should be ensured that PWM signal is applied through a proper soft-start sequence to minimize inrush current in the converter. Powering the module with a full duty cycle PWM signal already applied may lead to a number of undesirable consequences. If the DISB# is used similar caution is necessary to ensure proper sequencing with the PWM controller. Every time the power module is disabled through DISB#, there will be no output and the external controller may enter into open loop and put out a PWM signal with maximum duty ratio possible. If the DrMOS is re-enabled by simply taking DSBL# high, there will be extremely large inrush currents while the output voltage builds up again which may drive the system into current limit. There might be unpredictable consequences such as inductor saturation, overloading of input or even a catastrophic failure of the device. It is recommended that PWM controller be disabled whenever the DrMOS power stage is disabled or non operational for any reason. The PWM controller should always be enabled with a soft start to minimize stresses on the converter.

MODULE LOSS AND EFFICIENCY

Intel Rev 3.0 specifications impose fairly stringent limits on module loss and efficiency on DrMOS power trains. Under the specific boundary conditions of 12Vin /1Vout /25A (28A max) with operating frequency of 300 kHz to 1 MHz, the target for module losses is 6W maximum. The actual performance of AOZ5006 is shown in Fig. 1.

As with any SMT power device the so-called “rated current” of a DrMOS module is no indicator of its performance⁽¹⁾. It is misleading at best, and provided more for specsmanship than as a usable design parameter. Designers should instead look carefully at the projected module losses specified at their operating conditions. Datasheets give only typical values of these losses so a derating factor needs to be applied. If at all a rated current must be assigned, and there is absolutely no technical reason for doing it, look at the output current value at a loss of 6W. This is the limit set by Intel DrMOS specifications under all operating conditions. Most devices can deliver only 27-28A at 300 kHz within this power limit though their datasheets tout 35A current capability. The module loss for AOZ5006 is below 5W at 30A and 300 kHz as seen in Fig. 1.

USING RBOOT

The boost supply for driving the high side MOSFET is generated by connecting a small capacitor between the BOOT pin and the switching node VSWH. It is recommended that this capacitor CBOOT be connected as close as possible to the device across pins 4 and 15. Boost diode is integrated into the package. Fig. 2 shows RBOOT, an optional resistor used by many designers to slow down the turn on speed of the high side MOSFET. The value is a compromise to keep both the switching time and VSWH node spikes as low as possible and is typically 1Ω ~ 10Ω. Fig. 3 shows the impact of various values of RBOOT on VSWH voltage at V_IN = 12V, V_OUT = 1.2V @ 30A. The curves have been off set by 5 ns to get a clear picture. As RBOOT value is increased, the switching speed reduces and both peak voltage and ringing are reduced. However there is a penalty of nearly 0.4W in module losses from 1.5Ω to 20Ω. RBOOT does not impact the turn-off speed of the HS FET.

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