Designing with DrMOS, Part 1: Concept and Features

Feb 1, 2011 12:00 PM
Sanjay Havanur, Principal Applications Engineer Alpha and Omega Semiconductor

Find a downloadable version of this story in pdf format at the end of the story.

The synchronous buck converter has become the ubiquitous standard in electronic equipment. While the basic topology is rather simple, implementation has been evolving over the years to meet ever-increasing demand for higher efficiencies and power densities. Some of the major changes have been asymmetric differentiation of high-side and low-side MOSFETs, and the high-side FET optimized for ultra-fast switching and the low-side FET optimized for minimum conduction losses, integration of Schottky structures into the body diode of the low-side FET.

Recently, the popular SO-8 has given way to a variety of DFN and QFN packages which permit higher die sizes and better thermal interface within the same footprint. There is also a new class of power ICs which combine the PWM controller and the MOSFET in one package to offer compact and efficient power conversion solutions. However, the power ICs are somewhat limited in their scope, since the controller can have a small, fixed feature set and output current is also limited by the package. The recent DrMOS power modules (1) are an excellent solution optimized for high frequency power conversion at high output currens.

A major issue in improving the performance of synchronous buck converters has been the unavoidable presence of interconnecting inductances and resistances in the power stage. Today's converters switch at frequencies of hundreds of kHz where even a few nanohenries of stray inductance can affect the performance. Fig. 1 shows the sources of parasitic inductances in the input current loop of the synchronous buck converter. Most of them are due to bond wires, package pins and the minimal traces that are needed to connect different discrete packages. The gate loop inductances also contribute to slower switching, ringing, and in extreme cases shoot through conditions.

With low voltage MOSFET RDS(ON) values approaching 1 mΩ, the combined resistance of bond wires, pins and short traces adds up to a significant number. DrMOS eliminates most of these unwanted parasitics by integrating the power train and the driver in the same package. The pinout is further optimized so that input bypass capacitors may be placed very close to package leads for low inductance routing.

THE DRMOS CONCEPT

DrMOS is an acronym for Driver and MOSFET Module. It is a high efficiency synchronous buck power module consisting of two asymmetrical MOSFETs and an integrated driver. DrMOS was initially defined by Intel in 2004 as an 8×8 56 pin QFN package for the power hungry VRM modules(2). The driver section had a fairly wide menu of features including user defined drive voltages. However it wasn't well received in the PC market mainly because of cost and complexity. A smaller version in QFN 6×6 package with 40 leads and fewer logic features was proposed by Intel in 2007 under DrMOS Specification Rev 3.0(3). This new version is simpler and gaining wider acceptance among desktop, server, graphics card, gaming console and telecom power converter designers.

One main benefit of DrMOS is that the driver and MOSFETs can be closely matched as a single unit for optimum switching performance. A number of well-thought features are provided in the driver section making the DrMOS a highly versatile power module. A boot supply diode is integrated in the driver. The low side MOSFET can be driven into diode emulation mode to provide asynchronous operation when required. The PWM input is tri-state compatible, allowing both power MOSFETs to be turned off. The basic block diagram of the DrMOS module is shown in Fig. 2.

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