Bridgeless PFC Boosts Low-Line Efficiency

Feb 1, 2008 12:00 PM
By Jon Mark Hancock, Principal Engineer, Infineon Technologies, N.A., Milpitas, Calif.

Half-Wave Design

A bridgeless half-wave rectified dual boost PFC was proposed by Barbi and Souza that used insulated-gate bipolar transistors (IGBTs) with a nondissipative snubber to reduce switching losses.^[8] IGBTs lack the functional body diode of MOSFETs, so diodes must accomplish input half-wave rectification (slow-recovery diodes are sufficient). A modification of this design was adapted to MOSFETs, removing the nondissipative snubbers and adding diodes for bulk capacitor precharge (Fig. 4).

Diodes D5 and D6 are low-frequency half-wave rectifiers, alternately making a low-frequency connection between the ac line and the bulk negative connection. Diodes D3 and D4 provide the bulk precharge function during startup and in cycle skip or brownout recovery. The configuration of D3, D4, D5 and D6 forms a bridge and can be implemented with standard slow-recovery ac bridge rectifiers.

Chopper switches S1 and S2 drive inductors L1 and L2 on alternate line half cycles. This is a potential cost disadvantage compared with the combined coupled-inductor structure of the last example. However, by using separate cores high-frequency excitation and heating occurs for each inductor only during every other ac half cycle, providing thermal benefits that reduce inductor size and cost. Some half-wave rectification still occurs through the inductor and the MOSFET body diode, shown in Fig. 4, because they're not the primary half-wave rectifier used for other configurations.

The majority of current flows in diodes D5 and D6, slow-recovery half-wave rectifiers. This has the effect of reducing the power dissipation and maximum junction temperature in the MOSFET switches, which lowers their effective operating on-resistance (R_DSON). MOSFET R_DSON can double between room temperature and maximum operating temperatures, so a lower junction temperature lowers conduction losses.

In this configuration, current sense is at the same potential as the output load return and controller ground, allowing some flexibility in measurement technique and including the use of conventional resistive in-line sensing. Of course, resistive sensing increases the losses, but by how much?

Let's consider an example of a 1-kW output converter, assuming a nominal efficiency (η) of 90% and a low-input-line voltage of 90 Vac. Let's assume that for the controller being used, we need 26 mΩ to generate the required maximum sense voltage. The peak input current is:

The sense resistor power dissipation is:

This amounts to 0.5% efficiency loss at low line. However, if normal operation at high line and cost are a greater concern, at 208 Vac the total P_SENSE loss is only 0.755 W, less than 0.1%. This may be a tolerable tradeoff. Note that eliminating the extra diode drop of the conventional bridge diode even at high line may save 5 W to 8 W.

Examining this bridgeless PFC configuration, it could appear that the component count is double that of the conventional PFC configuration in Fig. 2a. In reality, with the same total MOSFET and boost rectifier silicon “budget” in either configuration, a higher total efficiency can be achieved with the bridgeless configuration. And considering the targets shown in Fig. 1, achieving higher efficiency at the lower power ranges is well served by splitting up the switch and diode budget between the dual boost phases.

To understand why this is so, examine the selection of the MOSFETs based on a conventional boost PFC that delivers the lowest total losses at full load and low-line ac. An Excel workbook was used to do this, with some assumptions translated from the data sheet to the application (Fig. 5a).

Fig. 5 shows an 800-W output PFC application, with a net input to output efficiency of 85%, which is used to factor up the required input power. The switching frequency is 130 kHz, with an input voltage of either 90 Vac in Fig. 5a or 208 Vac in Fig. 5b. The x axis is the nominal R_DSON specification, but this is not used for calculation; instead, the R_DSON is normalized to 105°C for the calculation of conduction losses.

Since turn-off losses can be made nearly negligible with super-junction MOSFETs^[7], the focus for dynamic losses is on C_OSS discharge at turn-on, an unavoidable loss in hard-switching circuits. With conventional diodes, this loss might be nearly swamped out by the Q_RR and C_OSS of the boost rectifier diode. With modern silicon carbide and even silicon ultrafast diodes, the output capacitance of the MOSFETs can play a dominant role in losses.^[9]

Looking at Fig. 5a, the minimum of the loss curve occurs for a specified R_DSON of 25 mΩ to 30 mΩ. At this point, at full load and low line, the conduction and switching losses are balanced and minimized. This low resistance would take two 75-mΩ TO-247 MOSFETs in parallel to achieve. This may not be the best way to achieve efficiency, particularly if we consider the bridgeless option. Those switching losses due to C_OSS capacitance will be there regardless of the load current or line voltage.

Considering that the bridgeless option can save 5 W to 8 W or more in conduction losses, we can take that savings into account in derating the conduction performance requirement for the MOSFETs. Moving on the loss line to the right, the losses increase as a function of conduction loss, so it's possible to move over to the right, where conduction losses are up by 5 W to 7 W, and write that off due to the conduction loss improvement of the bridgeless configuration.

Most importantly, shifting to a single 75-mΩ, instead of a 25-mΩ to 30-mΩ MOSFET cuts C_OSS switching losses in half. Therefore, switching loss reduction at all other load ranges and line voltages will be significant. This is shown in Fig. 5b for operation at full load at the SMPS normal operating 208-Vac input, where the optimum MOSFET choice would appear to be around 100-mΩ. In fact, if you have that so-called “optimum” conventional MOSFET of 25 mΩ to 30 mΩ for low-line performance in a conventional PFC circuit, the total losses at full load are doubled for the MOSFET, due to higher C_OSS switching loss when operating at 208 Vac. The loss is even worse at 50% load and below.

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References

1. Janick, J., “IBM Technology and Solutions,” IBM Power and Cooling Symposium, October 2007, Raleigh, N.C., proceedings at www-03.ibm.com/procurement.

2. Mitchell, D.M., “AC-DC Converter Having an Improved Power Factor,” U.S. Patent 4,412,277, Oct. 25, 1983.

3. Moriconi, U., “A Bridgeless PFC Configuration Based on L4981 PFC Controller,” Application Note AN 1606, STMicroelectronics, November 2002.

4. Hancock, J., “Meeting the Challenge for Offline SMPS Through Improved Semiconductor Current Density,” IBM Power and Cooling Symposium, 2005, proceedings at www-03.ibm.com/procurement.

5. Smith, K.M., Jr.; Lai, Z.; and Smedley, K.M., “A New PWM Controller with One-Cycle response,” IEEE Transactions on Power Electronics, Volume 14, Issue 1, January 1999, pp. 142-150.

6. Lu, B.; Brown, R.; and Soldano, M., “Bridgeless PFC Implementation Using One Cycle Control Technique,” IEEE Applied Power Electronics Conference (APEC) 2005 proceedings, pp. 812-817.

7. Bjoerk, F.; Hancock, J.; and Deboy, G., “CoolMOS CP: How to Make Most Beneficial Use of the Latest Generation of Super Junction Technology Devices,” AN-CoolMOS CP-01, www.infineon.com.

8. Souza, A.F., and Barbi, I., “High Power Factor Rectifier with Reduced Conduction and Commutation Losses,'' International Telecommunication Energy Conference (INTELEC) proceedings, June 1999, session 8, paper 1.

9. Lu, B.; Dong, W.; Shao, Q.; and Lee, F., “Performance Evaluation of CoolMOS and SiC Diode for Single Phase Power Factor Correction Applications,” IEEE APEC 2003 proceedings.