Bridgeless PFC Boosts Low-Line Efficiency

Feb 1, 2008 12:00 PM
By Jon Mark Hancock, Principal Engineer, Infineon Technologies, N.A., Milpitas, Calif.

A bridgeless input power factor boost converter offers the potential for higher efficiency to meet increasing demands for power savings, especially in switch-mode powersupply applications at low-line voltages.

Wide input-voltage range power factor correction (PFC) converters present some of the most difficult component challenges in ac-dc power electronics. With an input-voltage range that can extend from 265 Vac to as low as 75 Vac, the range of operating conditions is relatively extreme with wide current operating range and duty-cycle demands. As energy costs soar, the pressure is on to find ways to improve efficiency in power supplies used for applications such as telecommunications and computing. One solution is the bridgeless PFC technique.

Bridgeless boost PFC is a concept that has been long on promise for many years, but has not reached mainstream acceptance. Issues with EMI, robustness and the complexity of early configurations have stymied efforts to realize the bridgeless boost PFC converter's potential. Furthermore, improvements in components used in standard PFC boost converters have resulted in efficiency gains that did not justify the extra cost and complexity of the bridgeless configuration. And while bridgeless PFC has been viewed as a potentially useful technique to improve low-line input efficiency, it is not certain that is where the demand for improvement lies today.

As discussed in many forums over the last two years, the specification and evaluation of switch-mode power-supply (SMPS) systems is changing in response to the industry's desire to save energy in the real world. Traditionally, efficiency has normally been specified at full load for high- and low-line ranges, but now a more realistic approach is being widely adopted, looking at the behavior of the system and its efficiency in the range where the SMPS usually operates.^[1] This means that for redundant power systems such as computing servers and telecom power, it is now realized that efficiency in the 10% to 50% range must be considered along with full load behavior, as shown in Fig. 1.

As a result, system manufacturers such as IBM are changing the focus of how they specify and procure power. This change has been driven by customers with limited abilities to expand data centers because of power and cooling capacity. While the best of contemporary conventional PFC designs can just meet such current voluntary standards as Green Grid and ClimateSavers, more stringent future requirements may force designers to look for new solutions. A bridgeless PFC input configuration can help support these requirements, although it may require some rethinking of design methodology and optimization methods.

Conventional PFC Versus Bridgeless

The well-known single-boost PFC rectifier configuration shown in Fig. 2a consists of a full-bridge rectifier input, which provides a rectified pulsating half-sine waveform applied to a boost converter consisting of switch S1, boost inductor L1 and boost rectifier D1, which charges a bulk rectifier capacitor, “bus cap.”

Fig. 2b shows the basic bridgeless boost concept, patented in 1983.^[2] This variant shows a dual-winding inductor on one core. With alternating half-sine polarity on the ac line voltage, the MOSFETs alternate between operating as a low-frequency half-wave rectifier diode connecting the ac line voltage to the bulk bus negative terminal. It also operates as a high-frequency chopper driving the respective boost inductor winding and boost rectifier diode.

This configuration reduces the number of semiconductor devices in the inductor charging-current path from three to two, lowering conduction loss by about one diode-junction voltage drop (V_F ). The MOSFETs conduct as either a high-frequency switch or a low-frequency half-wave rectifier operating on alternate ac half cycles. As a result, some of the power losses normally handled by the ac bridge rectifier are now transferred to the power MOSFETs, potentially resulting in higher junction temperatures, which affects the overall MOSFET size.

Deterring the industry's adoption of the bridgeless PFC are several innate configuration characteristics. Because of the inductor configuration and lack of a low-frequency path to the output, there is a relatively high common-mode switching voltage present at the bulk negative connection and no low-frequency path to the ac input. This can result in relatively high common-mode EMI because of the charge and discharge of normal parasitic capacitances associated with the converter's physical construction.

Sensing the input voltage and input current usually require isolated circuits due to the high-frequency potential between the ac input and output ground reference. It may even be necessary to use dual current-sense transformers (for switch and inductor current), while also applying rectified half-sine voltage sensing on the primary.^[3] This example makes no provision for precharging the bulk capacitance or dealing with surge stress encountered during cycle skip or low-line to high-line jumps.

Hall Effect Current Sensing

A modified version of this configuration was used to develop an experimental high-efficiency bridgeless PFC front end in coordination with Isle Engineering, an independent consulting company in Ilmenau, Thuringia, Germany, up to a maximum output power level of 1500 W.^[4] Fig. 3 shows the basic configuration. Some of the design issues for this bridgeless PFC were addressed with specific techniques to optimize efficiency to the greatest extent possible, with a target value of 99% at full load. In practice, these efforts made it possible to realize about 98.8% efficiency at full output in the finished design.

First, input-voltage sensing was eliminated by using a PFC controller based on single-cycle control, as pioneered by Smedly and Cuk.^[5] This does not require input-voltage sensing and PFC controllers are available from vendors that use this technique.^[6] The LAH25 wideband Hall Effect sensor with isolated data outputs accomplishes current sensing on the ac primary after the bulk precharge diodes D3 and D4. This component avoids the losses associated with resistive sensing and eliminates the need for sensing transformers in high-speed switching paths.

The boost rectifier diodes are silicon carbide, merged PiN Schottky types that combine the characteristics of Schottky and p-n diodes with nearly negligible reverse recovery charge (Q_RR) capacitive losses and low forward drop. The switching MOSFETs were selected for low-energy-specified output capacitance (C_OSS) to minimize turn-on loss and are capable of near zero-voltage switching turn-off with very low losses due to their output capacitance nonlinearity.^[7]

The control arrangements for this configuration are somewhat complex, and a zero-crossing detector and driver-steering logic located after the PWM output of the PFC controller steer the driver signal to either S1 or S2. This depends on the ac-voltage input phase while driving the other MOSFET as a synchronous rectifier. A flyback bias supply, using an integrated controller and FET, provides ±12 V for the PFC controller and Hall Effect sensor module, which is part of the overall losses accounted for in the efficiency measurement.

This development was successful in demonstrating a range of techniques to achieve quite high efficiency in the PFC front end, but it was limited to a high-line configuration due to the lack of conventional heatsinks, and suffers from the common-mode EMI issues of the original configuration. Derivations of another proposed configuration address these issues.