Ultra-low Noise LDOs Optimize Load Performance

Jan 11, 2012 10:00 AM

Analog Devices, Inc. has introduced a pair of LDOs with low noise, high power supply rejection, and excellent line and load transient response. The ADP7102 and ADP7104 LDOs achieve a 15 µVrms fixed-voltage noise figure, power supply rejection ratio (PSRR) of 60 dB at 10 kHz in 3-V operation, and feature reverse current protection to guard against shorts and sudden load discharges. The new LDOs are designed to maximize the load performance and yield higher data conversion accuracy and resolution in high-frequency communications infrastructure, medical imaging, and industrial and instrumentation applications.

ADI’s LDOs are specially designed for noise-sensitive, high-performance loads typical of A/D and D/A converters, DSPs, FPGAs, precision amplifiers, high-frequency clocks, oscillators and PLL circuits, The new LDOs operate from 3.3 V to 20 V and are designed to regulate high-performance analog and mixed-signal circuits operating from 19 V to 1.22 V rails while achieving excellent line and load transient response with just a 1µF ceramic output. The ADP7102 has a maximum output current of 300 mA, while the maximum output current of the ADP7104 is 500 mA. Both LDOs are available in an 8-lead SOIC-EP and a space saving 3-mm x 3-mm LFCSP package, which provides excellent thermal performance for applications requiring up to 300 mA of output current in a small, low-profile footprint.

ADP7102 and ADP7104 LDO Key Features

• Reverse current protection
•  Low dropout voltage:
• ADP7102 = 200 mV at 300 mA load
• ADP7104 = 280 mV @ 500 mA load
• 7 fixed output voltage options: 1.5, 1.8, 2.5, 3, 3.3, 5, 9 V

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