DSCs Ease Migration to Digital Loop Control

Nov 1, 2006 12:00 PM
By Bryan Kris, Staff Architect, Architecture & Applications, Digital Signal Controller Division, Mic

Calculating Control-Loop Delay

Now that the major parameters of the design have been selected, the control-loop timing must be computed to get an idea of how the synchronous buck converter's power-conversion loop will behave.

In the SMPS design shown in Fig. 1, the ADC's sample-and-hold (S&H) circuit typically samples every 2 µs to 10 µs. The ADC converts the analog feedback signal to a digital value in approximately 500 ns. A wide variety of control algorithms are available to choose from, including the commonly used proportional, integral and differential (PID) algorithm. On a DSC, the PID controller program runs for about 1 µs to 2 µs.

By adding the system's ADC sample-and-convert time (500 ns), PID calculation time (1 µs), PWM output delay (0), transistor switching time (50 ns) and PID iteration rate period (2 µs), a total loop delay of 3.65 µs is derived. This implies a maximum effective control-loop sampling rate of 274 kHz.

While the Nyquist Theorem requires a 2x sampling rate to reconstruct a signal, digital control loops must sample at a 6x to 10x rate. A system with a 2x sampling rate introduces 180 degrees of phase-lag, from the sampling process alone. An 8x sampling rate reduces the phase-lag to 45 degrees of phase.

To maximize phase margin, many digital control systems oversample the analog signals by 10x or more. Assuming a maximum effective sample rate of 274 kHz, the effective control bandwidth is one-eighth of this value, or approximately 34 kHz.

Using the PID algorithm, the proportional, integral and derivative errors of the actual versus the desired output voltage are combined to control the PWM duty cycle. Thus, complex DSP programming skills are not needed to handle the DSP features of controller-centric DSCs (see the code listing in the box).

The central “core” of the control software (Fig. 2) is the PID loop, which is interrupt-driven by the ADC on a fixed-time basis. The PID loop is the most time-critical portion of the software and should never exceed approximately 66% of the available processor bandwidth. The remainder of the computing resources can be allocated to the idle-loop software. Typically, functions such as voltage ramp up/down, error detection, feed-forward calculations and communication-support routines must be performed in the idle loop.

Assuming 30 MIPS operation with the PID loop (comprising 30 instructions, the execution time is approximately 1 µs), if the iteration rate is 500 kHz (2 µs), then the PID workload consumes one-half of the available processor bandwidth, or 15 MIPS.

The power-stage components used in SMPS designs greatly affect the overall performance and reliability of the designs. In the case of the synchronous buck converter example, the selection of components such as the MOSFETs, inductor, and input and output capacitors will entail the same calculations as when a conventional analog control loop is employed.

For those interested in building the power-supply design presented here, the online version of this article provides a compressed file containing source listings, a hex file, Gerber files and a bill of materials.

DSP Programming Made Easy

This code listing shows an implementation of the PID algorithm on the dsPIC30F2020 DSC for a digital-mode buck converter. Although the PID software remains the same for most SMPS topologies, the initialization code may need to be modified for the peripheral modules.

; These registers are reserved for PID calculations
; w6, w7 = contains data for MAC operations
; w8, w10 = pointers to error terms, and gain coefficients
	COMPUTE_PID:
	push.s	; Save SR and W0-W3
	bclr.b IFS0+1, #3	; Clear IRQ flag in interrupt controller
	mov #PID_REG_BASE, w8	; Initialize pointer to PID register block
	mov #PID_GAIN_REG_BASE, w10	; Initialize pointer to PID gain register
	block
	mov ADBUF1, w0	; Read ADC to get voltage measurement
	mov COMMANDED_VOLTAGE, w1	; Get commanded output voltage
	sub w1, w0, w0	; W0 = proportional voltage error
	mov PROPORTIONAL_ERROR, w1	; Get previous voltage error
	sub w0, w1, w2	; diff error = new verr - old verr
	mov w0, PROPORTIONAL_ERROR	; Store New Proportional Voltage Error
	mov w0, PREINTEGRAL_TERM	; Store copy PERR as pre integral term
	mov w2, DERIVATIVE_ERROR	; Store new Derivative Error
	SUM_PID_TERMS:
	clr A, [w8]+=2, w6, [w10]+=2, w7	; Clear A, prefetch w6, w7
	mac w6*w7, A, [w8]+=2, w6, [w10]+=2, w7	; MAC proportional term and gain
	mac w6*w7, A, [w8]+=2, w6, [w10]+=2, w7	; MAC derivative term and gain
	mac w6*w7, B, [w8]+=2, w6, [w10]+=2, w7	; Update Integrator
	add ACCA	; Add ACCB (Integrator) to ACCA
	sftac A, -#8	; scale accumulator (shift)
	mov ACCAH, w0	; Read MSW of acca (result)
	btst ACCAU, #7	; Check sign bit of ACCA
	bra z, OUTPUT_PWM	; Branch if acca PWM value is positive
	clr w0	; Clear negative PWM values
	OUTPUT_PWM:
	mov w0, DC1	; Output new duty-cycle value
	pop.s	; Restore SR, w0-w3
	retfie	; Return from Interrupt

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