MCUs Heat Up Digital Loop Control

Aug 1, 2008 12:00 PM
By Tom Stamm, Applications Engineer, and Vipin Bothra, Power Electronics Applications Group Manager, STMicroelectronics, Schaumburg, Illinois

Initialization (Main Routine)

The two timers are set up first. The system clock frequency of 72 MHz increments the counters. Counter 4's terminal count is set to 72 to give a 1-MHz output. The threshold count is initially set to zero, to give 0 V out of the filter. The PID algorithm will modify this variable later.

The gate-drive outputs are held off until the last step of the initialization.

The initialization of Counter 1 is more complex. The timer is set to count up for 480 clock cycles and reset. The state of the gate-drive outputs must be programmed to zero for the reset state and the idle state, so the converter will not run until the control loop is ready.

When operating, CCP1's reference signal gives a rising edge at counter reset and a falling edge at a threshold count (240) to give 50% maximum duty cycle required by the converter. This could be increased somewhat, as dead-time subtracts from the actual on time.

The comparator on the power board feeds Counter 1's event trigger to terminate each cycle in advance of the threshold count. The event trigger is programmed to terminate the reference pulse on the first edge. Multiple transitions are not a problem.

In current-mode control, the current threshold and the rising current determine when the on period ends. In voltage-mode control, the current threshold is set above the maximum required load current. In either case the same hardware is used for peak current limiting.

PID Control Algorithm

The PID algorithm is implemented in integer math and runs once each 6.6-µs cycle, interrupt triggered by the Timer 1 terminal count reset. The execution time was measured at 4.4 µs, with the code written in C and not optimized. That leaves 2.2 µs still available in each cycle for other tasks, the equivalent of a 22-MHz processor. It is not even necessary to run the algorithm each cycle, if the control system can tolerate the added delay.

Fig. 8 shows a digital output (yellow) programmed to go high at the beginning and low at the end of the PID interrupt service routine, compared to the 6.6-µs power cycle (cyan). The output voltage is sampled just before the turn-on transient (first rising edge of cyan trace) in the dead-time interval.

The PID C routine was later compiled with the “Optimize for Speed” option set. The calculation time dropped from 4.4 µs to 1.8 µs.

Debugging

The timer routines were debugged without the power board. Everything possible was checked before connecting the two boards. In addition, a removable fuse was added to one of the power transformer primary connections. With the fuse removed, all the gate signals could be safely tested with power applied to the board.

The ADC was checked with an external power supply. The current-limit comparator and PWM current compare source were checked in the same way.

The fuse was then inserted, and the system debugged in operation. Several fuses and a few synchronous rectifier MOSFETs were sacrificed in learning about the gate-driver delay time.

The PID routine's gain constants were adjusted using the seat-of-the-pants method. The gain margin had to be increased to accommodate the discontinuous-conduction mode at low load current. This could have been done in software, but we haven't gotten there yet. Fig. 9 shows the demo's transient response with a 2-A transient on a 1-A load.

Two factors contribute to poor current limiting at low output voltages (near short circuit): delay in the gate-driver chips (mentioned previously) and leading-edge spike on current waveform at the burden resistor.

The system is less stable when in discontinuous-conduction mode. This still needs work.

Overshoot on turn-on was a serious problem. It was solved by adding a conditional call to the PID algorithm. The method used is to call a separate routine to drop and slowly raise the output-voltage setpoint if the output voltage is measured to be below a percentage (90%) of the operating setpoint.

The output voltage is measured each cycle. If it is below 90% of the setpoint, the setpoint is reduced to 10% of the correct value, and incremented periodically by 10% until the output is within the correct range. Overshoot still exists, but it's smaller; ugly, but effective.

References

1. UM0427 STM32 user manual.
2. STM32F103x6, STM32F103x8, STM32F103xB data sheet.
3. RM0008 reference manual.
4. AN2580 STM32F10xxx TIM1 application examples.
5. UM0426 STM3210B-EVAL evaluation board user manual.

Core: ARM 32-bit Cortex-M3 CPU

• 72-MHz maximum frequency,
• Single-cycle multiplication and hardware division

32 kbytes to 128 kbytes of Flash memory and 6 kbytes to 20 kbytes of SRAM
Clock, reset and supply management
Low power with sleep, stop and standby modes
2 × 12-bit, 0 V to 3.6 V, 1-µs ADCs (up to 16 channels)
7-channel DMA controller supporting timers, ADCs, SPIs, I ² Cs and USARTs
Up to 80 fast I/O ports
Debug mode
Up to 7 timers
Up to 9 communication interfaces
CRC calculation unit, 96-bit unique ID

Click here for the enhanced PDF version of this article

Acceptable Use Policy blog comments powered by Disqus