MCUs Heat Up Digital Loop Control

Aug 1, 2008 12:00 PM
By Tom Stamm, Applications Engineer, and Vipin Bothra, Power Electronics Applications Group Manager, STMicroelectronics, Schaumburg, Illinois

Housekeeping and MCU Power

A simple 3-W flyback converter sources isolated +5 V and +15 V to the system. Its implementation is not important to this discussion; it is part of the power board.

The MCU operates from 3.3 Vdc, derived from a low-dropout regulator on its demo board. The 3.3-V supply is used as a reference voltage for the system; precision was not required for the demonstration, but a precise regulator could be used. The MCU only requires 30 mA to operate; supply loading does not compromise its precision.

The gate drivers used were far from optimum for a 150-kHz converter. They exhibit about a 500-ns delay, which gives excellent noise immunity in their intended motor control application, but the delay is a bad choice here. Both turn-on and turn-off times delay drive to the FETs. The turn-off delay creates some problems with current limiting at low duty cycles, with the output short circuited.

Comparator U7 generates a digital signal for cycle-by-cycle peak current-mode control or for current limiting in voltage-mode control. The comparison signal is an analog voltage derived from a 1-MHz pulse-width modulation (PWM) timer output from the MCU.

A ribbon cable carries all signals and power between the power board and the MCU board. Table 2 lists these interface signals. Fig. 5 shows the circuits between the MCU and the power converter's synchronous rectifiers.

It is worth noting that the 12-in. ribbon cable did not create any problems. Try that distance with an analog control chip.

Use of On-Chip MCU Peripheral Components

Only three peripherals implement the control functions. Fig. 6 illustrates the flow chart and the resulting waveforms produced by the MCU to drive the synchronous rectifiers.

Timer 4 generates a 1-MHz PWM signal that is filtered to a dc voltage for the peak current comparator. The PWM scheme is far from ideal for the task. The filter causes a significant delay after changes in the duty cycle. This could be reduced by having a digital-to-analog converter (DAC) loaded with a new value as each calculation cycle completes. (Planned versions of the MCU will have the digital to analog and an on-board comparator.) A 72-MHz system clock generates the PWM signal, giving a granularity of 1/72 of the maximum voltage. This could have been halved; a frequency doubler is available for the counter. It was not necessary, however, because the power-filter components still limit performance.

Timer 1 is a 16-bit timer that generates the complementary drive signals required by the synchronous rectifiers and primary MOSFETs. It includes four capture-compare (CCP) registers, of which only one is used in the demo. The timer and CCP generate a reference 150-kHz, 50% duty cycle waveform. The current comparator's changing state can also terminate the waveform's on time. A dead-time generator at the CCP output prevents overlap of the on time of the shunt and series synchronous rectifiers. You can optimize the dead-time for different conditions of load, line and temperature, or it can be adjusted by a self-optimizing background control loop.

While the use of this timer is gross overkill for setting the switching frequency, the fine granularity of the dead-time adjustment, 13.9 ns, was used to advantage. To maximize efficiency, the dead-time was adjusted to give minimum input power with a fixed 80% load.

The fine granularity of this timer also can be advantageous if voltage-mode control is used. Again, if necessary, the timer's granularity can be decreased to less than 7 ns by doubling the 72-MHz clock frequency. This could be useful in reducing audible noise from limit-cycle oscillations.

The MCU contains two 12-bit analog-to-digital converters (ADCs). One measures the system output voltage. Only one analog input is used of the 10 available. It is anticipated that another will be used when implementing a current-sharing scheme. The fast 1-µs conversion time allows a sample to be taken at a known point in the power cycle, where switching noise is at a minimum.

This processor core contains a 32-bit single-cycle hardware multiplier, which greatly reduces PID calculation time. Several multiplications are needed in the PID algorithm. It was not necessary to minimize their number by rearranging the algorithm.

Firmware

The entire firmware development was done in C. The code is compiled in a laptop. Fig. 7 lists the PID algorithm's pseudo code, which occupies only six lines of C code.

Flash memory on the µC holds the program and initialization constants. When programming starts, the MCU stops and its output pins go to a high-impedance state, stopping the forward converter.

A debug pod handles the programming with the system powered and live. Programming takes only 15 seconds to 20 seconds, then the reset button on the MCU board is pressed and released. The program starts and the forward converter comes to life.

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