Graphical System Design: A Bridge to Digital Power

Mar 1, 2007 12:00 PM
By Gustavo Castro, Staff Analog Engineer, and Luke Schreier, Product Marketing Manager, National Ins

Using LabVIEW, this algorithm can be implemented quickly, and it works under a set of conditions defined by the designer. Examples of such conditions are low voltage across the linear stage, or output-parameter changes requested from the user.

This feed-forward algorithm has been added as a case structure in Fig. 7. The output then becomes an open-loop control that can boost the switcher power to the maximum. This is the equivalent to a step function, but the feed-forward algorithm could actually be any arbitrary function to fit a particular operation; it can be either a self-contained, closed-loop process or the result of a different process.

Once these modifications to the algorithm have been implemented in LabVIEW and simulated on the host PC, they can be deployed to the FPGA that controls the power supply for final validation and system integration.

During cross-system validation, other issues that force further tweaking of the algorithm may arise. Taking the previous example, in the case of using a step function for the feed-forward algorithm, an excess of input current may blow input fuses or affect overall system performance. To limit this input current, the step function can be substituted with a ramp function (or another soft-adjust function) that is not so fast it blows fuses or exceeds the current rating (Fig. 8) and not so slow it fails to address the transient-response problem that existed for intermediate voltages.

Design Deployment

Adjusting this ramp time can be as simple as changing a variable until the current spike does not go above the limit set by the system ratings or other design constraints. You can do this in real time by manually changing values in the host PC while running the hardware-in-the-loop simulation. When the desired value has been found, the algorithm can be redeployed to the FPGA for final verification.

Therefore, if output is close to collapse or the user changes output parameters, then:

P = KP 3 (SP[n] - PV[n])

I = KI 3 (SP[n] - PV[n]) + KI 3 (SP[n-1] - PV[n-1])

D = KD 3 (PV[n] - PV[n-1]).

OUTPUT = ramp function, else OUTPUT = P + I + D.

The main advantage of using LabVIEW FPGA for simulation and hardware-in-the-loop testing is the ability of the analog engineer to rapidly change and then deploy the model to the FPGA for production. As electrical, mechanical and thermal constraints continue to challenge power-supply engineers, this flexibility offers a real-world solution to difficult digital-control implementations.

Want to use this article? Click here for options!
© 2007 Penton Media, Inc.