Graphical System Design: A Bridge to Digital Power

Mar 1, 2007 12:00 PM
By Gustavo Castro, Staff Analog Engineer, and Luke Schreier, Product Marketing Manager, National Ins

Designing the Control Loop

Having identified an appropriate algorithm for control logic (PID) and an effective form of loop control (power-based), it's now possible to design the digital control loop. The implementation of a digital algorithm in an FPGA can require several lengthy iterations among the tasks of mathematical definitions, simulations, review by the analog and digital engineers, and testing. Using this labor-intensive process to discover and correct design bugs can be quite time consuming.

Hardware-in-the-loop simulation has helped reduce development time through a PC-controlled process that serves as a substitute for one or several portions of the final design. The goal is to have the computer simulate several scenarios (stimulus and control algorithms) before the design is actually deployed into the real application. This improves the debugging, validation and overall cost of implementation.

LabVIEW FPGA offers a method for achieving hardware-in-the-loop simulation. The power of a graphical programming and modeling language allows for quick prototyping and deployment into real-world applications. For digitally controlled power supplies, this means that digital control systems can be prototyped and tested in a computer without concerns about FPGA size or the time required for the process of writing and synthesizing large volumes of VHDL code. After the graphical code has been validated and tested, it can be deployed onto an FPGA directly from LabVIEW, so the control loop runs entirely independently from computer software in the actual application.

Consider the power-control scheme of the power supply shown in Fig. 5. The power-control approach takes care of the low- to high-power transients, but not medium-power transients. During medium-power transients, there are already smaller voltages across the linear regulation stage, and the output impedance of the switching stage is higher than in the previous example. Under these conditions, it is still possible to collapse the voltage across the linear stage, so a modification to this algorithm is in order.

Because of the limited sampling frequency, the PID controller may not be fast enough, as it is going to lag for at least one sampling period before it can respond to this type of transient. If the time constant imposed by the output impedance of the switcher and the load is faster than the sampling period, collapsing of the output occurs as shown in the PID control waveforms in Fig. 6.

However, providing a solution is very simple once the controller is in the digital domain, because it only requires the addition of a feed-forward algorithm. The feed-forward algorithm leads the PID in transients, increasing the power to the maximum so the output never collapses. The PID can then regulate to reduce the power. These actions can be seen in the PID with feed-forward waveforms in Fig. 6.

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© 2007 Penton Media, Inc.