Boost Converter Efficiency Through Accurate Calculations

Sep 1, 2008 12:00 PM
By Travis Eichhorn, Senior Applications Engineer, National Semiconductor, Grass Valley, Calif.

Comparing the calculated values with measured values using the higher-order model requires that a converter be used that operates in either the CCM or the DCM. Unfortunately, the LM3528 operates in a pulse-skip mode to improve efficiency at light loads. This would require a third equation to model the converter in this mode. Additionally, using a white LED driver adds an extra layer of complexity in the calculations since the LED voltage changes with I_OUT.

To remedy this, the LM27313 standard asynchronous boost converter will be used to compare the calculated versus measured results of the efficiency estimations (Fig. 2). This converter operates in either the CCM or the DCM over the entire load current range, thus providing a more direct comparison with the developed higher-order model.

Fig. 3 and Fig. 4 use the equations developed so far for the first-, second- and higher-order models to calculate D and solve for efficiency versus output current. The LM27313's output voltage is held at 19 V over the entire load current range of 0 mA to 40 mA (Fig. 2).

Fig. 3 compares the first-order model, the second-order model, both with and without switching losses, the higher-order model and the measured efficiency. Fig. 4 also compares the measured efficiency with the calculated efficiency using the higher-order model as previously described, and the higher-order model that is slightly modified to account for changes in C_D and C_DS capacitive energy losses at very light loads.

The first-order model again uses the ideal duty-cycle ratio and calculates efficiency at each I_OUT. Both second-order models (for dc losses only) and second-order switching losses use the F(D²) equation and solve for D at each I_OUT using the quadratic formula. The higher-order model uses C code and iterates through the F_CCM(D⁵) equation by varying D between 0 and 1 while testing for the first zero crossing. At the end of each F_CCM(D⁵) iteration, a comparison is done between the calculated inductor current ripple and the average inductor current to determine when:

When this happens, the converter is assumed to be in the DCM, and the F_DCM(D³) equation is then iterated to calculate D. This is done at each I_OUT to generate the efficiency graph.

As would be expected, the first- and second-order (dc only) models show a lot of variation between the calculated and actual efficiency. The second-order model, which includes switching losses, is the closest at low currents while the higher-order model is closer at high currents, but tends to deviate at low currents when the device operates further into the DCM.

This can be explained by understanding how the boost-circuit capacitances charge and discharge each switching cycle as the boost converter transitions from the CCM to the DCM. When the converter is operating fully in the CCM, the drain-to-source and diode capacitances charge and discharge from zero to V_OUT, each cycle causing a power loss of:

As the converter transitions from the CCM to the DCM (i.e., the load current decreases), the inductor current slope will hit zero before the end of the switching period. If the inductor current hits zero well before the end of the switching period, the inductor current will begin to go negative, causing the energy in the switching node capacitances to return back to V_IN. As the load current is further reduced, the dead time increases and a damped ringing develops between the switching node capacitances and the inductor. Eventually this voltage ringing will decay to V_IN.

The result is that as the converter transitions more and more into the DCM, the switching node capacitances will give a lot of their energy back to the input and essentially have to charge up to a smaller and smaller voltage. At the extreme minimum current, when the switching node has discharged down to V_IN before the start of a new switching period, the drain-to-source and diode capacitance power loss becomes closer to:

If the third-order DCM equation is made to reflect this, then the efficiency versus load current becomes closer to the actual efficiency at light currents (Fig. 4). The discontinuity in the modified higher-order plot occurs at the CCM/DCM boundary where the C_DS and C_D capacitance voltage begins shifting from V_OUT down to V_IN.

Another source of error that was left out of the duty-cycle calculations is that due to inductor switching losses (core loss and eddy currents). This would tend to decrease the efficiency even further when the converter operates in the DCM due to the large current ripple. Unfortunately, inductor ac switching-loss values are not commonly given, so they were not used in these examples.

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