We generally associate the Power Distribution Network (“PDN”) with the power circuits used to drive CPUs and FPGAs.  The increasing use of FPGAs in our products certainly means that at some point we will all need to be fluent in PDN.  In reality, PDN applies to all circuits and not just FPGAs and CPUs. Even everyday glue logic, such as high speed CMOS gates can wreak havoc in a PDN.  The ultimate results of poor PDN design range from non-functional circuits in cases where the PDN fails to maintain adequate voltage regulation to the high speed circuit, to noisy circuits, where the PDN noise flows through the system through various distribution paths, such as PCB crosstalk or regulator PSRR.  While understanding and optimization your PDN can require a great deal of effort, including expensive 3D simulations, the fundamental concepts can be simply stated in five key points.

Keep it flat

Most PDN books tell you that the best performing PDN impedance looks flat over frequency.  That is because noise signals are generated as a result of discontinuities or impedance peaks in the PDN.  The PDN is comprised of resistance, inductance and capacitance associated with the PCB traces and planes, the decoupling capacitors and their parasitics and the package parasitics including the bond wires and die capacitance of the high speed devices.  Minimizing the Q of these resonant circuits is the key to obtaining a flat impedance.  One of the fundamental PDN management tools is target impedance. This is the impedance below which all peaks should be maintained for good performance.  The target impedance concept may have significant flaws [1], but it is still the most common PDN design technique in use today.  However, the more basic goal should be to maintain the impedance as flat as possible up to a bandwidth that is dependent on the edge speed of the load signals, the amplitude of the dynamic current change and the impedance of the PDN.  Note that this is the edge speed and not the pulse repetition frequency dependent.

Impedance matching is key

Test equipment manufacturers have understood this relationship for many decades.  The use of a matched source and a matched load, connected through a matched cable is not an accident.  The most common impedance in use is 50Ω though there are other less common impedances, such as 75 Ohms for TV applications.  The reason for this is that the lowest PDN impedance occurs when the source and load impedances are exactly equal.  Matching the interconnect impedance, the load impedance and the source impedance are really just another way of saying keep it flat, as any mismatch will result in either increased capacitance or inductance, either of which are undesirable.

Low rates have higher probability of issues

While it might appear that the higher the signal frequency, the more prominent the PDN issue might be, this is not always the case.  The increased signal frequency certainly does carry with it an increase in signal integrity concerns, but not necessarily for the PDN.  The reason that the lower frequencies are a bigger issue is simple.  Looking at a low duty cycle pulse we will see every harmonic of the pulse frequency and with somewhat constant amplitude.  For example, a 100kHz clock signal introduces signals with spectral content that are 100kHz apart.  Increasing the pulse frequency to 1MHz results in spectral signals that are 1MHz apart.  The likelihood of finding a PDN resonance very close in frequency to a spectral signal from the pulse is much greater with the lower frequency pulse rate.  We can see this clearly using a 100kHz pulse and a 1MHz pulse as shown in Figure 1 and Figure 2.

Figure 1
Figure 1 - Pulse and spectral content for 100kHz rate

Figure 2
Figure 2 - Pulse and spectral content for 1MHz rate