SPICE circuit simulations are a powerful design tool to analyze a system's immunity against conducted EMI surge voltages. SPICE can serve as a valuable tool to validate and optimize the performance of surge-protection circuits using transient-voltage-suppression (TVS) avalanche diodes. The small size, fast response time, low clamping voltage and low cost of TVS diodes provides for an effective solution to solve surge problems. A comparison of SPICE simulations with bench tests demonstrates the ability of TVS avalanche diodes to clamp the surge voltages caused by noise sources such as inductive devices and load switching.

I Versus V Characteristics

Zener and TVS avalanche diodes have similar electrical characteristics; however, there are significant differences between the two devices. A zener is designed to regulate a steady-state voltage, while a TVS diode is designed to clamp a transient-surge voltage. In addition, TVS diodes typically have a larger junction area than a standard zener, which provides the ability to absorb high peak energy. The current versus voltage relationship of a TVS diode is shown in Fig. 1.

The graph in Fig. 1 depicts various diode parameters. IF is the forward current and VF is the associated forward voltage at that current. IR is the reverse leakage current and VRWM is the reverse-working voltage at IR. Typically, VRWM (typ.) ≅ 0.8 × VBR. Other parameters include IT, the test current; VBR, the breakdown voltage at IT; and IPP, the maximum reverse peak pulse current. IPP is typically specified with either the 8 × 20-µs or 10 × 1000-µs surge pulse. In addition, VC is the clamping voltage at I PP.

TVS Diode SPICE Models

The majority of the TVS avalanche diode SPICE models available are created with the SPICE “D” diode statement. There are several restrictions that limit the accuracy of using the diode “D” statement to model a TVS avalanche diode.

First, the diode statement does not have a provision for defining a separate series resistance for the forward- and reverse-bias breakdown regions. The resistances in the two regions are not equal; thus, it is not possible to accurately model the slope of the current versus voltage characteristic in both regions. Next, the “D” statement does not have a variable to model the variance of the breakdown voltage with temperature. Table 1 provides the variables available with the PSPICE “D” diode model.

Macro-Model Subcircuit

A TVS diode macro-model offers several advantages over the standard diode model available in SPICE, including a more accurate representation of the breakdown characteristic. TVS macro-models are created by combining standard SPICE devices into a subcircuit. Fig. 2 shows a schematic for a macro-model of a TVS avalanche diode. A PSPICE netlist for this model appears below. This particular netlist models the NUP2105, a dual, bidirectional voltage suppressor from Phoenix-based ON Semiconductor (Fig. 3).


*NUP2105 PSPICE macro-model

*Bidirectional TVS avalanche diode, SOT-23, VBR = 26.4 V

*Model simulates 1 of the 2 bidirectional TVS devices


*DA Cathode = 1, DB Cathode = 2, DA,B Common Anode = 3

.SUBCKT NUP2105 1 2 3

*Bidirectional devices are formed from two unidirectional


X1 3 1 HALFNUP2105

X2 3 2 HALFNUP2105



*Model HALFNUP2105 represents one bidirectional pair

*of a dual device

*Anode = 7, Cathode = 1


*Forward Region

*D1's CJO term models the capacitance

D1 2 1 MDD1

.MODEL MDD1 D IS=1.83708e-14 N=1 XTI=1 RS=0.2

+ CJO=26.4e-12 TT=1e-08


*Leakage Region

*RL models leakage current (IL)

*MDR temp. coef. model ΔIL / ΔT

RL 1 2 MDR 4.32244e+08



*Reverse Breakdown Region

*RZ models the ΔI / ΔV slope

RZ 2 3 1.28

D2 4 3 MDD2

.MODEL MDD2 D IS=2.5e-15 N=0.5

*Breakdown Voltage (VBR) = IBV × RBV

EV1 1 4 6 8 1

IBV 0 6 0.001

RBV 6 0 MDRBV 26357.1

*MDRBV temp. coef. model ΔVBR/ΔT


D3 8 0 MDD2

IT 0 8 0.001


*L models the lead-to-silicon connection

*package inductance

*L is distributed between two diodes for

*bidirectional diodes

L 7 2 1.24e-9




The TVS macro-model is based on the zener diode model provided in references 3 and 4. References 1 and 2 provide additional information on modeling TVS devices.

Forward bias region: Diode D1 is the key component when voltage VD is greater than zero. The TVS diode's forward-bias characteristics are controlled by D1's saturation current (IS), emission coefficient (N) and series resistance (RS) variables. The forward-bias current equations are as follows:

Leakage region: The leakage or reverse bias before breakdown region is defined when voltage VD is between 0 V and the breakdown voltage (VBR). Currents IF and IR are small in comparison to IL because diodes D1 and D2 are reverse biased; thus, the leakage current is approximated by VD/RL:

Breakdown region: The breakdown region is modeled by EV1, D2 and RZ. Current flows through this path when the voltage exceeds EV1 plus the forward voltage of D2. The breakdown voltage (VBR), represented by EV1, is equal to the product of current source IBV and resistor RBV, minus the voltage of D3. D3 is used to compensate for the voltage drop of D2. The clamping voltage (VC), specified at current IPP, is equal to the sum of the voltages of EV1, RZ and D2:

Impedance characteristics: The transient response of the macro-model is simulated by including the TVS device's impedance versus frequency characteristics. It is necessary to model the impedance because the fast rise time and high peak current of the surge pulse creates high-frequency information that influences the transient performance of the clamping response.

The impedance plot of a TVS avalanche diode is shown in Fig. 4. The measured impedance can be modeled by an equivalent circuit that consists of resistor (RS), inductor (LS) and capacitor (CS) connected in series. RS is equal to the real portion of the complex impedance and is measured at the resonant frequency (fR). At fR, the impedance is purely resistive because the impedance of the LS and CS are equal in magnitude but opposite in polarity.

CS is obtained by measuring the capacitance at 1 MHz. LS is obtained from the resonant frequency, which corresponds to the minimum impedance. Table 2 provides a correlation of the small signal model to the SPICE macro-model.

Modeling the inductance ensures the magnitude of the overshoot pulse due to the inductance (V = L (ΔI/Δt)) of the IC package is simulated. Matching the capacitance helps in predicting the shape of the clamped waveform, while including an accurate resistance term is important in predicting the power capability of the device.

Simulation Test Results

The ability of the SPICE macro-model to predict the performance of a TVS device is shown by comparing simulation and bench data for the 8 × 20-µs and 10 × 1000-µs surge tests. These waveforms are often used to specify the power rating of a TVS device, in addition to representing the surge pulses produced by common noise sources. The surge pulses are defined by their rise time (tR), measured at 10% to 90% of the pulse amplitude, and their pulse duration, measured at 50%. The voltage and current waveforms represent the open- and short-circuit — that is, R = 2 Ω — conditions, respectively.

Fig. 5 shows the clamping performance of a TVS diode for the 8 × 20-µs surge test. The 8 × 20-µs surge pulse represents the positive voltage transient created by the sudden interruption of current in a load that is connected in parallel with an electronic module. Low-side drivers that are used to turn on electronic modules, motors and relays are examples of systems that can produce this surge pulse.

The clamping performance of a TVS diode for the 10 × 1000-µs surge test is shown in Fig. 6. The 10 × 1000-µs surge pulse occurs when power is removed from an inductive load and the device under test (DUT) simultaneously. The DUT remains connected in parallel with the inductance, which produces a negative surge voltage. DC motors, solenoids and relays are common examples of inductive loads that can produce this surge pulse.

The discrepancy between the measured and simulated 10 × 1000-µs clamping voltage is due to the self-heating of the device by the surge current. In addition, the macro-model was calibrated to the 8 × 20-µs pulse instead of the 10 × 1000-µs pulse.

The accuracy of the predicted clamping voltage for high-energy, long-duration surges can be improved by calibrating the model with the 10 × 1000-µs pulse. Future enhancements of the macro-model will include integrating a thermal model to simulate the increase in the TVS device's junction temperature due to self-heating.

Macro-models provide an accurate SPICE representation of the TVS avalanche diode's current and voltage characteristics for most applications. The macro-models solve several of the limitations associated with the SPICE diode “D” statement and the curve-fit models. Macro-models provide a powerful design tool to analyze surge suppression circuits; however, they are not a replacement for hardware development tests. A summary of the limitations of the macro-models is shown in Table 3.

Enhancing System Reliability

System designers are being challenged to meet stringent surge-suppression requirements. In order to produce competitive products, they must increase the reliability and reduce the size and cost of their circuits. TVS avalanche diodes can be used to increase the surge immunity without significantly adding to the cost, size and complexity of power circuits. The ability of TVS diodes to dissipate surge voltages that contribute to the early failure of semiconductors can be evaluated using SPICE macro-models.


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