Fig. 1, from JESD22-C101F, shows a generic CDM test circuit. It includes a discharge head with a pogo pin, a 1 Ω radial resistor, the top ground plane, a semi-rigid coaxial cable, and the test head support arm. The test head is robotically driven, and it often has two small cameras that are used to align the test head in the correct position over the device under test (DUT). The potential of the DUT is raised by the field-induced method. A test voltage is applied to the field-charging electrode. The DUT sits in the “dead bug” (pin up or ball up configuration) on an FR-4 dielectric that covers the field-charging electrode. Once the DUT has been charged, the device is discharged by having the pogo pin touch each DUT pin, one at a time. At least one positive and one negative discharge is applied to every DUT pin. If the DUT no longer meets its data sheet specifications after the CDM stress, it is considered to be a failing unit.

Fig. 1.     Generic CDM Circuit

The CDM tester is verified to be in spec by using a 1 GHz/5 Gigasamples/sec oscilloscope to measure the current-versus-time waveform when the DUT is one of the standard JEDEC capacitors. The specifications for the small and large disk capacitors are found in the JEDEC CDM specification, JESD22-C101F. The generic discharge waveform is shown in Fig. 2.

Fig. 2.     CDM Discharge Waveform

To be in spec, the waveform must have characteristics that meet the requirements defined in a Table of the CDM specification

CDM Test Variability

In the CDM test, it is relatively easy to raise the field-charging electrode to the proper voltage. Unfortunately, the correct voltage on the charge plate is insufficient to guarantee a repeatable CDM event. Most of the variability in the CDM test comes from the discharge event. The sources of variability include the following:

·     JEDEC test head differences

·     Waveform measurement

·     Charging time

·     Size of ground plane

·     Pogo pin variables (size, cleanliness, etc.)

·     Capacitor disk

·     1 Ω radial resistor

·     Humidity control (<60%)

Most of these sources of variation can be characterized or controlled. Although no two JEDEC test heads are alike, the test head differences can be electrically modeled. The charging time can be controlled by the CDM system software. The ground plane can be manufactured to tight tolerances. The correct type of pogo pin can be obtained, and the pogo pin can be cleaned before every test run. The capacitor disk can be cleaned before each use. The 1Ω radial resistor can be measured accurately with a four-point probe, and the software that analyzes the waveform can take the measurement into account when computing Ip. Flowing dry nitrogen in the CDM chamber provides humidity control and a more repeatable result.  Even if these issues are resolved, however, there still is the challenge of system-to-system variation caused by differences in oscilloscope resolution.