DSP-Based 20-bit Quasi-Absolute Encoder Suits Low Speed

May 1, 2009 12:00 PM
LEE WEI YAN, Applications Engineer, Avago Technologies, San Jose, Calif.

A DSP design approach, including hardware and software implementation for a quasi-absolute encoder.

A high-accuracy 20-bit resolution quasi-absolute encoder with DSP-based signal processing is housed in a dc stepper motor assembly, as shown in Fig. 1. Able to operate in a temperature range between 0°C to 90°C, it is intended for closed-loop control systems that require high precision and repeatability, as well as reliable performance — even in a high temperature environment.

The encoding signals are provided by a 3-channel analog optical encoder and a 1,024-line code disk with an index track. The index marks are located at different intervals. The encoder finds its absolute position by scanning two consecutive indexes.

The high-speed DSP chip implements real-time signal conditioning, 1,000 times software interpolation and factory-programmed error calibration. The encoder output has a final resolution of 1,024,000 counts and an angular position accuracy of ±0.05° (mechanical degree). Absolute position is available as a 20-bit binary data through a serial peripheral interface (SPI).

ENCODER MODULE

The encoder module operates on a single 5-V supply. An on-board 3.3-V voltage regulator supplies current to the DSP and amplifier blocks. A 10-pin connector provides the interface to connect to the end application system for controlling the SPI communication and stepper motor drive. (Fig. 1)

The encoder's sine and cosine analog current outputs are amplified by a pair of transimpedance amplifier circuits for interpolation by the DSP. The amplified signals then are sampled by two built-in high-speed analog-to-digital converter (ADC) channels. Here, the amplifiers' gain and offset voltage are set to match the ADC's 3.3-V range. The rail-to-rail op-amp enables single-supply operation while providing high bandwidth and dynamic range for the input signal from ground to the supply voltage.

Amplified analog signals also are directed through a pair of threshold circuits to generate digitized versions of the signals that are 90 electrical degrees out of phase. These digitized signals then are further directed into the DSP's quadrature decoder hardware circuit that drives an internal counter, allowing the DSP to use the incremental signals to track the encoder's rotation angle and direction and synchronize it with the index pulse triggering.

DSP BLOCK

The DSP controller is a 16-bit fixed-point DSP core with special hardware and peripherals optimized for motor control applications. The 50-ns instruction cycle time offers 10 times to 20 times the speed of traditional 16-bit microcontrollers and microprocessors, thus allowing high-speed real-time algorithms. (Equations)

The SPI is configured to operate in slave mode to interface with the user application (master). A read-out cycle is initiated by the master by pulling the Encoder Select (CS) line low, generating an external interrupt (Fig. 2). The DSP branches to an interrupt service routine (ISR) where the entire encoder algorithm and SPI routine is handled. The transmission length is always 16 bits. It takes two consecutive transmissions to read the encoder's 20-bit position data (high-byte comes first, then low-byte).

The maximum readout rate available from the encoder is 20 kHz. This is due to the 50-µs latency required by the DSP to process the position data. The serial transmission is synchronized by the clock pulse (CLK) at a maximum frequency of 1 MHz. A parity bit is included for each transmitted byte. The status bits indicate absolute mode/incremental mode and high byte/low byte (Fig. 2).

For resolution higher than the grating lines of the code disk, the encoder position within a grating line is determined by software interpolation. The electrical angle between 0 to 360 electrical degrees around the Lissajous circle (Fig. 3) is given by:

Where,

H0 = Sin value sampled by the ADC

H1 = Cos value sampled by the ADC.

For fast computational speed, the interpolation algorithm uses a lookup table to implement the arc-tan function.

Offset, gain and phase errors occur in the encoder signals due to misalignment and other non-idealities. These affect the overall accuracy of the encoder when the analog signals are interpolated. The offset and gain corrections are done in real-time by sampling the analog signals and tracking the errors. Phase error is not compensated in real-time but is corrected by a constant calibration factor programmed at the factory.

Rotary encoders are affected by eccentricity issues due to concentricity and assembly tolerances (Fig. 4). The angular error resulting from eccentricity is given by:

Where,

ε = Eccentricity error

Rop = Optical radius.

Over one revolution of the code disk, the eccentricity is periodic and is a sinusoidal function of the shaft angle (Fig. 5). The position error as a function of angle of rotation is given by:

ΔP = (ε/Rop) × Sin(A) × (180/π) mech.deg.

Where,

A = angle of rotation (relative to position error of zero).

To achieve ±0.05° (mechanical degree) accuracy, the allowed eccentricity is:

ε (allowable) = ε × Rop = 0.05 × (π/180) × 11.5 mm = 10 µm.

This places a high constraint on assembly tolerance. Because eccentricity translates directly into mechanical position error rather than error in the signals, it cannot be compensated by signal conditioning. However, this problem is corrected by software calibration at the factory during assembly.

At power-up, the encoder starts up in incremental mode. Absolute mode is achieved by recognizing the unique distances between the index marks on the code disk. The indexing algorithm needs to find two consecutive indexes and compares them against a lookup table stored in the flash memory to determine the absolute position.

The indexing initialization can start from anywhere and at either direction. Absolute mode is found after a small rotation within a maximum initialization angle of 136° (mechnical degree).

Fast processing is possible with a high-performance DSP integrated with high-speed ADC and hardware capture inputs. The overall software overhead is optimized to give a fast readout rate of 20 kHz by using algorithms based on lookup tables (arc-tan interpolation and eccentricity correction). The real-time offset and gain correction compensates for signal imperfections to enable high 1,000-times interpolation factor for 20-bit total resolution. The software error calibration (eccentricity correction) feature ensures ±0.05° accuracy over the entire 360° rotation and eliminates the need for accurate mechanical alignment during assembly.

This encoder application is best suited for closed-loop control systems demanding high precision and repeatability with operational speed up to 240 rpm (for example, high-resolution surveillance cameras, robotics, semiconductor handling systems, and factory automation).

REFERENCES

“Avago Super High Resolution 20-Bit Quasi-Absolute Optical Encoder Datasheet,” October 2007.

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