PCB Layout: The Final Weapon In The Power Designers'Arsenal

May 17, 2007 2:00 PM
by Alan Elbanhawy, director in the Advanced Power System Center, Fairchild Semiconductor International, San Jose, Calif.

Another consideration concerning parasitic resistance is that the higher the frequency of the switched current, the higher the resistance. If we take into consideration switching frequencies of say 1 MHz, this means that the current’s fundamental frequency is 1 MHz, while the rest of the harmonics are at multiples of this frequency. When the duty cycle is low, these harmonics can extend into hundreds of megahertz and each harmonic has its respective parasitic resistance.

Parasitic inductance is the twin of parasitic resistance when considering the influence of the layout on the performance of a given power converter and the entire system. The effects of parasitic inductance range from increases in EMI to excessive losses caused by shoot through in MOSFETs to catastrophic failure of the power switches. The last problem could result from inductance-induced ringing that causes the switches to exceed their maximum rating.

In this last case, particularly with mass produced designs, if the parasitic inductance cannot be reduced to an obviously safe level, I would recommend using Extreme Value Analysis. This methodology can verify that, under no combination of tolerances, will the switches fail.

The dependence of parasitic inductance on frequency is the opposite of parasitic resistance (i.e. the inductance decreases when the frequency is increased.) Several physics-based, finite-element software packages now available in the market can help with these calculations. Then too, there are the old reliable simple formulas that can give you a reasonable estimate of the size of the problem—or lack thereof.

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