Package Parasitics Influence Efficiency

Nov 1, 2005 12:00 PM
By John (Bang Sup) Lee, Senior Staff Application Engineer, Vishay Siliconix, Santa Clara, Calif.

Careful consideration of inductive and resistive losses in device packaging will contribute to a design’s overall efficiency.

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As the dc-dc conversion industry proceeds toward the demand for improved power density and efficiency, thermally enhanced packages with SO-8 footprints have been gaining prominence and popularity in dc-dc converter designs. These packages bring thermally superior, higher power devices to the SO-8 footprint, enabling more efficient designs with a reduced profile. However, package parasitic effects in the standard SO-8 are not clear due to various MOSFET characteristics such as threshold voltage (V_TH), package parasitic inductance, on-resistance (R_DS(ON)) change, driver capability and layout.

But, by utilizing the efficiency data and switching waveforms of nearly identical silicon operating in SO-8 and Siliconix's PowerPAK SO-8 packages in a two-phase synchronous buck converter, the package parasitic effects become more apparent. The results show that the package parasitic effect mainly depends on the package parasitic inductance and the MOSFET R_DS(ON) shifts from increased junction temperatures (T_J) determined by thermal characteristics of the package.

Package Comparison

The PowerPAK SO-8 utilizes the same footprint and pinout as the standard SO-8, as shown in Fig. 1. The only difference is the extended drain connection area. This allows the PowerPAK SO-8 to be substituted directly for a standard SO-8 package. The bottom of the die-attached pad is exposed to provide a direct, low-resistance thermal path to the substrate on which the device is mounted. This decreases the thermal resistance between the foot of the PowerPAK and the printed-circuit board (PCB).

A basic measure of a device's thermal performance is the junction-to-foot thermal resistance (R_{θ_JF}). This parameter is measured with the device mounted to an infinite heatsink and therefore is a characterization of the device only; in other words, the device is independent of the properties of the object to which it is mounted. The PowerPAK SO-8 package has a junction-to-foot thermal resistance of 1°C/W. This parameter is 13°C/W for the standard SO-8 package. The PowerPAK has thermal performance equivalent to the DPAK and an order-of-magnitude better thermal performance over the SO-8, assuming that the silicon devices are identical in both the PowerPAK SO-8 and standard SO-8 packages. Again, the PowerPAK SO-8 package allows heat to dissipate directly from the bottom of the package because the underside of the drain lead-frame is directly exposed, resulting in a lower junction-to-foot thermal resistance.

In the SO-8 package, cooling is less efficient because of the presence of the mold compound that covers the top and bottom of the silicon. In this package, the majority of the heat is dissipated through the mold compound into the PCB and the air.

Fig. 2 shows a cross-sectional view of the PowerPAK SO-8 and standard SO-8 packages. As shown in the figure, the drain and source lead-frame length in the PowerPAK SO-8 is thinner than the standard SO-8. That's why the PowerPAK SO-8 has a reduced height and package inductance compared to the standard SO-8. Using simulations of the two package types at direct current, 100 kHz and 1 MHz yielded parasitic inductances of 0.5 nH, 0.3 nH and 0.24 nH, respectively, for the PowerPAK SO-8 package. The same values for the standard SO-8 were 2.21 nH, 2.12 nH and 1.79 nH.

Device Characteristics

To explore the difference in performance between the two packages, identical die were assembled in a PowerPAK SO-8 package and a clip-attached SO-8 package. Devices for both packages were selected carefully wafer-to-wafer to minimize parameter variations. The MOSFET parameters for the selected devices are shown in the table.

For the standard SO-8 packages, the Si4336 was chosen for the low-side MOSFET, and the Si4390 was chosen for the high side. The selected Si4336 and Si4390 devices were screened to keep variations within 5% in the SO-8 package. The same screening was conducted for the devices mounted within the PowerPAK SO-8 package (Si7336 for the low side and Si7390 for the high side).

Test Circuit Description

The test circuit used to evaluate a performance comparison in the PowerPAK SO-8 and standard SO-8 was a two-phase synchronous buck converter. There were two high-side devices per phase and two low-side devices per phase, totaling eight MOSFET devices on the board. The circuit accepts an input voltage of 12 V to 19 V. The output voltage was 1.3 V, and a voltage of 5 V was applied to the gate-driver supply. An automatic efficiency test tool was used to characterize efficiency and loss in the test platform. The automatic efficiency tool monitored all necessary node voltages and line currents for the efficiency calculation. The tool acquires data by performing 10 samplings for a given load condition. For each measurement, the maximum and minimum values are removed from the data set, and the average value of the eight remaining samples is then taken as the actual value of the measurement. The tool allows the converter to run for 500 sec for thermal stabilization of the board prior to executing efficiency and temperature measurements.

Fig. 3 shows the finished demo board. The PCB was a two-layer, 2-oz copper board sized at 14.9 cm × 8.7 cm. While the converter was designed as a four-phase synchronous buck, only two phases were used in the test. A 0.68-µH output inductor was selected to optimize performance of the switching regulator. A smaller value would have caused a high-inductor ripple current that would have resulted in lower efficiency. A larger value would have slowed the transient response of the pulse-width modulated controller. Schottky diodes typically placed across the low-side MOSFETs were omitted to ensure an accurate comparison of the performance between the SO-8 and PowerPAK SO-8 package types.

PowerPAK SO-8 and SO-8 Efficiencies

Neither a heatsink nor a forced airflow were used for the measurements of the package parasitic effects. Practical switching frequencies of 300 kHz and 500 kHz were chosen because they are widely used in VRM and point-of-load applications. The converter packaged in the PowerPAK SO-8 showed higher efficiency than the one in the SO-8 package. In Fig. 4, the PowerPAK SO-8 efficiency was 0.8% higher than that of the SO-8 at 43 A. The difference in efficiency between the two packages increased with frequency. This indicates that the PowerPAK SO-8 package is more efficient than the SO-8.

Conduction Loss in Low-Side Device

There are two major sources of loss in dc-dc converters. One is conduction loss; the other is switching loss. The conduction losses result from R_DS(ON) of the devices and may be calculated by I_LOAD² × R_DS(ON) × D for the high-side MOSFETs, and I_LOAD² × R_DS(ON) × (1 - D) for the low-side devices, where D is the duty cycle and equals 10.8%. The change in MOSFET R_DS(ON) with temperature must also be taken into account, since the R_DS(ON) increases by the factor of 1.3 at T_J=100°C (Fig. 5).

Fig. 6 shows the foot temperature measurements on the low-side devices, taken close to the source terminal of the devices on the PCB. Although this is not an absolute measurement of the junction temperature, it is a close approximation. The results show that the PowerPAK SO-8 is 91°C, while the standard SO-8 is 101°C, where V_IN = 19 V, V_OUT = 1.3 V, f_SW = 500 kHz and I_LOAD = 43 A. The standard SO-8 die temperature is 10°C above the PowerPAK SO-8. Using the junction-to-foot thermal-resistance characteristics of the PowerPAK SO-8 and the standard SO-8, the silicon's R_DS(ON) would be 1.25 × R_DS(ON) for the PowerPAK and 1.3 × R_DS(ON) for the standard SO-8 under the same condition of I_LOAD = 43 A, as shown in Fig. 5, which applies because the sum of the two drain currents equals the load current of 43 A. Each drain current is then 21.5 A, which is sufficiently close to 25 A. Thus, the conduction loss R_DS(ON) in the PowerPAK SO-8 is 4% less than the loss in the standard SO-8 package. The conduction loss affected by the package temperature under the conditions of V_IN = 19 V, V_OUT = 1.3 V, f_SW = 500 kHz and I_LOAD = 43 A can be calculated as follows:

The measured total losses in the standard SO-8 is:

P_{LOSStotalSO-8} = 12.71389 W (Eq. 1)

The conduction loss of the low side in the SO-8 can be calculated as:

The measured total losses in the PowerPAK SO-8 is:

P_{LOSStotalPowerPAK}=12.25391 W (Eq. 3)

The conduction loss of the low side in the PowerPAK SO-8 is:

Now, the total-loss deviations caused by the package difference between the standard SO-8 and PowerPAK SO-8 is:

(Eq. 1) - (Eq. 3) = 0.45998 W
(Eq. 5)

The conduction-loss deviations caused by the package difference is:

(Eq. 2) - (Eq. 4) = 0.055 W
(Eq. 6)

Now we can calculate how much conduction loss contributes to the total-loss deviations between the two packages:

Therefore, the difference between the low-side conduction loss in the PowerPAK SO-8 and the standard SO-8 is 12% of the difference between the total losses for each package type. It is assumed that the remaining 88% is due to dynamic losses caused by package parasitic inductance and thermally shifted threshold voltages.

Package Parasitic Inductance Loss

As stated previously, the PowerPAK SO-8 has a package parasitic inductance of 0.3 nH at 100 kHz, while the standard SO-8 has 2.12 nH at 100 kHz. The package parasitic inductance increases switching time, resulting in greater switching losses in the SO-8 compared to the PowerPAK SO-8. The switching waveforms in Fig. 7 show that, as expected, the use of the PowerPAK SO-8 package results in a lower peak voltage and less ringing, having 14 cycles compared to 15 cycles in the standard SO-8 package.

Another aspect of device packaging that must be taken into consideration is the impact thermal characteristics will have on the MOSFET V_TH. When V_TH decreases, the MOSFET switching speed increases, resulting in reduced switching loss. From Figs. 6, 7 and 8, the V_TH of the low-side MOSFET is decreased by -0.35 at 74°C and by -0.5 V at 84°C, where the conditions are V_IN = 12 V, V_OUT = 1.3 V, f_SW = 500 kHz and I_LOAD= 43 A. For the high-side MOSFET, V_TH is decreased by -0.25 V at 74°C and by -0.35 V at 84°C.

Assuming that all capacitance values remain constant over temperature, the dynamic losses caused by the package parasitic inductance and thermally induced shifts in VTH have the greatest impact on the converter's efficiency.

The End Result

Efficiency for a given package is mainly a function of the package parasitic inductance losses, V_TH change and how package thermal properties affect the low-side MOSFET conduction losses. The conduction loss caused by thermal increases to R_DS(ON) in the low-side MOSFET is a major factor that contributes 12% of the difference between the respective total losses in these packages. The remaining 88% of the difference between the two package types is mainly from the difference in thermal changes in VTH and parasitic inductance, which is responsible for the observed ringing and peak voltages. Overall, the PowerPAK SO-8 shows a 0.8% greater efficiency over the standard SO-8 package.

References

1. Pavier, Mark, et al. “High Frequency DC-DC Power Conversion: The Influence of Package Parasitics,” IEEE APEC 2003.

2. Xiao, Y., et al. “Analytical Modeling and Experimental Evaluation of Interconnect Parasitic Inductance on MOSFET Switching Characteristics,” IEEE APEC 2004.

3. Cronje, W.A.; Van Wyk, J.D.; and Van Wyk, J.D., Jr. “A Systematic Approach to Modeling of Layout Parasitics in Converter — Initial Formulation,” Proc. of IEEE Power Electronics Specialist Conference 1998, pp. 1944-1950, 1998.

4. Ejury, J., and Elbanhawy, A. “Investigations of the Influence of PCB Layout Parasitic Inductances in DC-DC Converters on the Efficiency,” International PCIM Europe Conference 2004, pp. 31-36.

5. Nobauer, G., Ahlers, D., and Sevillano-Ruiz, J. “A Method to Determine Parasitic Inductances in Buck Converter Topologies,” International PCIM Europe Conference 2004, pp. 37-41.

SO-8	Part Number	RG (Ω)	CISS (F) at 15 V	CRSS (F) at 15 V	VTH1 (V)	RDS(ON) (Ω) at 10 V	RDS(ON) (Ω) at 4.5 V
Low side	Si4336DY	1.33	5.40E-09	4.02E-10	2.16E+00	2.30E-03	2.95E-03
	Si4336DY	1.29	5.51E-09	4.08E-10	2.23E+00	2.27E-03	3.05E-03
	Si4336DY	1.31	5.42E-09	3.90E-10	2.19E+00	2.30E-03	2.98E-03
	Si4336DY	1.33	5.47E-09	3.68E-10	2.15E+00	2.40E-03	3.02E-03
High side	Si4390DY	0.97	1.49E-09	8.98E-11	1.53E+00	6.98E-03	9.68E-03
	Si4390DY	0.97	1.50E-09	9.08E-11	1.59E+00	6.98E-03	9.68E-03
	Si4390DY	0.93	1.52E-09	9.00E-11	1.64E+00	6.98E-03	9.83E-03
	Si4390DY	0.92	1.53E-09	9.06E-11	1.72E+00	6.98E-03	9.83E-03
	Si4390DY	0.92	1.53E-09	9.05E-11	1.62E+00	6.91E-03	9.68E-03

PowerPAK SO-8	Part Number	RG (Ω)	CISS (F) at 15 V	CRSS (F) at 15 V	VTH1 (V)	RDS(ON) (Ω) at 10 V	RDS(ON) at (Ω) 4.5 V
Low side	Si7336DP	1.30	5.49E-09	3.88E-10	2.21E+00	2.10E-03	2.91E-03
	Si7336DP	1.29	5.48E-09	3.96E-10	2.18E+00	2.21E-03	2.91E-03
	Si7336DP	1.30	5.48E-09	3.85E-10	2.16E+00	2.26E-03	2.93E-03
	Si7336DP	1.28	5.54E-09	3.85E-10	2.16E+00	2.22E-03	2.93E-03
High side	Si7390DP	0.96	1.48E-09	8.96E-11	1.67E+00	6.75E-03	9.66E-03
	Si7390DP	0.95	1.48E-09	9.02E-11	1.67E+00	6.72E-03	9.60E-03
	Si7390DP	0.96	1.50E-09	8.97E-11	1.57E+00	6.75E-03	9.54E-03
	Si7390DP	0.96	1.49E-09	8.82E-11	1.60E+00	7.04E-03	9.94E-03

Table. MOSFET data used for the selected devices.