Control Method Solves Low Duty-Cycle Dilemmas

Sep 1, 2006 12:00 PM
By George Hariman, Circuit Design Engineer, and Chris Richardson, Applications Engineer, National Se

Valley-Current-Mode Control

A few years ago, an article described how leading-edge valley-current-mode control is able to overcome the shortfall of the trailing-edge peak-current-mode control.^[4] Leading-edge valley-current-mode control does solve the problem of being able to regulate to very low high-side FET on-time requirements. However, it also has some disadvantages and may be the reason why few commercial buck regulators employ this control method (Fig. 3).

It is well known that subharmonic instability will occur for trailing-edge peak-current-mode control when the duty cycle is bigger than 50%.^[2] To optimally solve this problem, a compensating slope with magnitude equal to the downslope needs to be added to the sensed upslope.^{[5, 6]} For leading-edge valley-current-mode control, the converse is true. That is, for leading-edge valley-current-mode control, subharmonic instability will occur when the duty cycle is less than 50%.

Figs. 4 and 5 depict how subharmonic instability in leading-edge valley-current-mode control occurs. It is evident that this first fact will cause a problem for the intended application at hand — very low duty-cycle operation. To optimally solve this subharmonic instability, a compensating slope with magnitude equal to the upslope now needs to be added to the sensed downslope.^{[5, 6]} For very low duty-cycle operation, the upslope is naturally much larger than the sensed downslope and, thus, generation of the compensating slope may be difficult to achieve.

Another disadvantage of leading-edge valley-current-mode control is its poor line regulation for buck switching regulators. In trailing-edge peak-current-mode control, it is easy to employ input voltage feed-forward as the inductor current upslope has an input voltage term, which is dominant for low duty-cycle applications, to it. However, for leading-edge valley-current-mode control, this is not the case, because the inductor current downslope does not depend on input voltage at all. Therefore, leading-edge valley-current-mode control has worse line regulation than trailing-edge peak-current-mode control.

Emulated Peak-Current-Mode Control

Emulated peak-current-mode control^[7] addresses the challenge of low duty-cycle operation by maintaining a control loop much like that of trailing-edge peak-current-mode control but with the advantage of valley-current-mode control. It achieves the latter benefit by measuring the valley-current information across the low-side FET on-resistance or sense resistor. This valley information is then used to emulate the inductor current upslope to obtain peak-current information.

Like traditional trailing-edge peak-current-mode control, the emulated-current-mode control requires slope compensation on the emulated upslope (Fig. 6). Since methods of doing this have been perfected for trailing-edge peak-current-mode control, implementation of slope compensation on the emulated current-mode control is trivial.

An example of a buck switching-regulator controller employing the emulated-peak-current-mode control is the LM3495 from National Semiconductor. It is able to operate jitter free to produce very short high-side FET on-time.^[8]

Fig. 7 shows a typical application circuit to regulate 1 V from a 12-V input voltage running at 500 kHz for a 7-A load. The LM3495 also employs input voltage feed-forward on the emulated upslope to improve line regulation.^[8] Fig. 8 shows a captured waveform of the switch node and inductor current at very low high-side FET on-time.

Other features of the LM3495 include a guaranteed feedback accuracy of ±1% at output voltages as low as 0.6 V, the ability to synchronize to an external clock, the ability to startup into a prebiased output and the ability to track from another power supply for power-up sequencing.

Since there is no blanking associated with the high-side on-time, in theory, emulated peak-current-mode control allows the on-time of the high-side FET to go to zero. However, in practice, the on-time is limited by propagation delays and other timing in the PWM logic. The most prominent propagation delay would be the delay from the PWM logic output to the driver and to the high-side FET. Excessively short on-time may result in the high-side FET turning on improperly, resulting in jittery operation. With the LM3495, the minimum on-time (which can be achieved with a particular application circuit) is 50 ns. This performance is depicted in Fig. 8.

References

1. “LatticeSC FPGA Family,” Lattice Semiconductor datasheet.

2. Erickson, R., and Maksimovic, D., Fundamentals of Power Electronics, 2nd edition, Kluwer Academic Publishers, 2001.

3. “LM3075 High Efficiency, Synchronous Current Mode Buck Controller,” National Semiconductor datasheet.

4. “Valley Design Techniques Outperform Peak Current-Mode Approach for CPU Supplies,” PCIM Power Electronics Systems magazine (now Power Electronics Technology), July 2001.

5. Sheehan, Robert, “Emulated Current Mode Control for Buck Regulators Using Sample & Hold Technique Small Signal Linear Analysis,” Power Electronics Technology Exhibition & Conference, October 2006, National Semiconductor.

6. Interviews with Robert Sheehan, principal applications engineer, National Semiconductor.

7. Tomiyoshi, Kenji. “Apparatus and Method for Step-Down Switching Voltage Regulation,” U.S. patent #7,045,993, National Semiconductor.

8. “LM3495 Emulated Current Mode Control Controller,” National Semiconductor datasheet.

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