PFC Circuit Halts Inrush Currents

Jun 1, 2008 12:00 PM
By John Bottrill, Senior Applications Engineer, Texas Instruments, Manchester, N.H.

A Closer Examination

The first thing the designer needs to realize is that the total energy stored in the output capacitor is the minimum energy that is going to be dissipated in the combination of Q3 and R5 of Fig. 3.

Resistor R5 is chosen first to have the 110% of the maximum allowable current through it, if the voltage across it is equal to the maximum rectified input voltage (V_INMAX). At the higher input voltages, R5 will be dissipating most of the energy each time the converter has power applied (Fig. 4).

If the resistor is sized to handle the energy (0.5 × C_PFC × V_INMAX²) and the instantaneous voltage of V_INMAX, then one should have no problem with the turn-on. Since this is a one-of voltage pulse that will last only milliseconds, the requirements for the resistor are that it be capable of absorbing the energy pulse, that it can withstand the voltage and that there be no long-term need for thermal dissipation.

Next, R1, R2 and R3 are chosen. R1 is chosen so that the voltage across it is greater than the V_BE of Q2 at full load, but with very little margin. For these simulations, R1 was chosen to drop 1 V at 110% of the rated current. R2 was set to 650 Ω and R3 to 350 Ω so that at the maximum current, the base of transistor Q2 would be 0.65 V. Therefore, at 110% of the maximum load, the transistor Q2 would be turned on and start to pull down on the gate of Q3. As the voltage on Q3's gate is pulled down, Q3, which is in the active region, increases its impedance. This decreases the current flowing through it, limiting the current to the desired 110% limit.

This means that Q3 is dissipating power that will raise its junction temperature. As the voltage across the output capacitor increases, the voltage across Q3 and R5 will drop. This results in R5 carrying less current. Because of the active nature of the circuit, Q2 will carry more current, so that the total is 110% of the maximum load current (Fig. 5).

Fig. 5 shows that the total current charging the capacitor is at the 110% level whenever the input voltage exceeds the voltage that is already stored on the capacitor. Fig. 4 adds the power lost in R5 and Q3 to the plot showing the power in each device.

As can be seen in Fig. 4, there is approximately 600 W of power being dissipated in the junction of the pass transistor Q3 for approximately 7 ms on the first half-cycle alone.

An IRFP450 FET is now examined for this application. The information needed is contained on the instantaneous thermal impedance graph (Fig. 6). The graph shows that for a pulse of 7 ms, the junction temperature increases by 0.15°C/W. This means that with the power predicted, there will be a 90°C temperature rise from the first pulse.

The second pulse has almost as much power. And the third one adds a significant contribution. This pushes the temperature well over 200°C. If two of the FETs are paralleled, the temperature rise drops in half — but the impact on the cost is significant, and the temperature rise still might exceed the maximum junction temperature.

There are several options to prevent this level of heating. Limiting the current through the FET at higher voltages is the first and most obvious. This can be done by adjusting the ratio of R2 and R3, and by increasing the value of R1. Each of these has the desired effect of lowering the power in the FET's junction by combining both results for better overall performance.

By changing R1 to 0.175 Ω, R2 to 1 kΩ and R3 to 100 Ω, the energy lost in the first half-cycle of the line input current is spread over two pulses — each approximately 2 ms in duration and peaking at about 170 W. This averages out at (0.5 × 170 W × 2 ms) × 2 over 8.33 ms, or 40 W average over 8.33 ms for a temperature rise of 6°C for the first pulse, compared to 90°C in the previous condition.

The second pulse has the same additional power as the first pulse. The power in the subsequent pulses is higher as follows: the third at 90 W, the fourth at 91 W, the fifth at 61 W and the sixth at 26 W. This total power added and averaged over the start-up cycle results in a temperature rise at the junction of 105°C.

Remember, this power is for the full charge of the capacitor — not just the first half-cycle of the sine wave, so it looks like the junction is at a higher temperature than in Fig. 5 where it went up 90°C in the first 8 ms. This is still going to stress the FET. Thus, the resistance of R1 probably should be increased further to get the temperature down further. This will depend on the program derating requirements and ambient temperature conditions.

Nothing is free, and the downside of this is that the time to charge the PFC capacitor to the maximum line voltage is changed from 40 ms to 60 ms. Moreover, resistor R5 will have to absorb the additional power. This power loss is shown in Fig. 7.

The bottom line is that care must be exercised when selecting the resistor, because the instantaneous power is as significant as the voltage across it. It will probably be better if two or three resistors are used in series.

Once the PFC starts, this circuit can either be shorted out by a relay circuit or by another FET that is put across Q3 and R1.

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