Capacitor Ripple Current Improvements

Aug 1, 2004 12:00 PM
By Jim Drew, Hardware Engineer VII, Hewlett-Packard, Marlboro, Mass.

The multiphase buck regulator topology allows a reduction in the size of the input and output capacitors versus single-phase designs. By quantifying the input and output currents, designers can determine the requirements for the input and output capacitors.

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In the conventional dc-dc converter buck topology (Fig. 1), power from the input voltage source is transferred to the output filter by turning on the pass transistor. When the pass transistor is on, the voltage across the output inductor is the difference between the input voltage and the output voltage, causing the inductor current to ramp up and store more energy in the inductor. While the current through the inductor is below Io_avg, the capacitor is supplying the additional load current. When the inductor current is greater that Io_avg, the additional current through the inductor recharges the output capacitor.

After a predetermined time, Ton = Tp*(Vo/Vin), where Tp is the period of the switching frequency, the pass transistor is turned off and the shunt transistor is turned on. The voltage across the inductor is now minus Vo, resulting in a downward slope in the inductor current. The inductor is now transferring its stored energy to the load and continues to charge the output capacitor, until the inductor current becomes less that Io_avg.

The shunt transistor remains on during the time period of Toff =Tp - Ton. As a result, the input current through the pass transistor of the conventional dc-dc converter buck topology (Fig. 1) is a clipped trapezoidal waveform (Fig. 2), which is the composite of the load current and the inductive ramp current of the magnetic elements in the load current path.

The period of this current waveform is the output switching period of the pass transistor. The duty cycle is related to the ratio of the output voltage to the input voltage. Because the switching frequency of the dc-dc converter is beyond the response time of the input source and the power distribution system, this current must be supplied by the input capacitor of the dc-dc converter. The RMS current drawn from the input capacitor and (to a lesser degree) the ripple voltage across the input capacitor are key factors determining the selection of this capacitor.

The output capacitor usually is determined from the output ripple voltage specification, whose major influencing factor is the output inductor ripple current (Fig. 3) flowing through the effective series resistance of the output capacitor. In low-output voltage applications, the required output ripple voltage is only met by increasing the size of the output inductor, lowering the output ripple current or paralleling many output capacitors.

The output impedance of the converter is the square root of the ratio of the output inductance and the output capacitance. Increasing the size of the output inductor is generally a poor choice because of its effect on the output impedance, transient response and its physical size. Paralleling of output capacitors results in reducing output ripple voltage and output impedance.

Multiphase Topology

Fig. 4 shows the basic circuit of each channel, while Fig. 5 shows a 4-channel system. Each channel's switching cycle is delayed in time by the channel switching period divided by the number of channels. Evaluating the ratio of the input voltage to the output voltage to the nearest integer is one method to define the number of channels, resulting in the lowest output ripple current.

In the multiphase topology, the load current is the sum of the average channel currents. Evaluating the ratio of the total output current to the channel current to the nearest integer is another method to define the number of channels, which may result in a higher output ripple current. For a multiphase converter with four channels with each channel switching at 250 kHz, the switching period would be 4 µs and each channel would be time-delayed by 1 µs. This would result in an output and input current ripple frequency of 1 MHz.

The effect of time delaying is that the input current waveform changes from a clipped trapezoid to a sawtooth shifted by a dc component (Fig. 6), when the product of the number of channels and the channel duty cycle is an integer. When the product is less than one, it remains a clipped trapezoid but at a frequency of four times the channel frequency. In all other cases where the product is greater than one but not an integer, the waveform is a modified saw-tooth plus a dc component (Fig. 7). The output current triangular wave amplitude also is reduced. In fact, the output current triangular wave amplitude is reduced to zero resulting in only a dc component, when the product of the number of channels and the channel duty cycle is an integer.

The design equations used to determine the input and output currents, as well as for the selection of the input and output capacitors, can be found below. The scalars n₁ (the integer of the number of phases times the duty cycle of the channel plus one) and n₂ (the number of phases minus n₁) are used to define the number of rising and falling slopes respectively from the channel output current seen in the system's output ripple current for various duty cycle ranges.

The scalar n₃ (n₁-1) is used to define the two duty cycles (DL and DH) of the modified sawtooth waveform of Fig. 8. The scalars n₃ and n₄ (n₃ -1, if negative use 0) are used to calculate the peak and the lower midpoint of the input current, by determining the number of rising slopes from the channel input current seen in the system's input current for various duty cycle ranges. Ton_out is the time duration of the rising slope of the output ripple current.

Design Example

The results of a design example will be presented for a nonisolated buck converter whose input is a 5-V source and whose output is 1.65 V at 50 A. It will be assumed that the conversion efficiency will be 80% and the channel operating frequency (f_ch) will be 250 kHz. The first case will use the conventional, single-channel, buck converter, and that design will be compared to a 5-channel multiphase converter. We'll use the same inductance in both designs; therefore, the current ramp (δI_ch = 8 A) will be the same. The input and output capacitors will consist of a 470 µF 10-V capacitor that has an ESR of 60 mΩ, an ESL of 1 nH and and RMS current rating of 1.826 A at 85°C.

If we assume the conduction losses in the FETs are the dominant power losses, we can calculate the maximum allowable Rds(on) and the on time (Ton_ch) of the buck FET. We'll select a FET with an Rds(on) of 5 mΩ.

Based on the output ripple voltage requirements, we can select the number of required capacitors with the following expression. The required number of capacitors will be rounded up to the next integer — in this case, 17.

The number of input capacitors will be selected based on the capacitor ripple current requirements. The peak current (Ipk_ch) in the channel is 14 A, while the average input current is 19 A. The input RMS (Iin_RMS) and the capacitor RMS (Ic_RMS) currents can now be calculated. The capacitor RMS current is 24.311 A, which sets the number of input capacitors to 14.

Table. Comparison of conventional buck topology to the multiphase buck topology.

	Iout	δIout	ICoRMS	Co	Iinavg	IinRMS	ICinRMS	Cin
Conventional Topology	50 A	8 A	2.308 A	17×470 uF	19.0 A	30.855 A	24.311 A	14×470 uF
Multiphase Topology	50 A	0.611 A	0.176 A	2×470 uF	19.0 A	19.347 A	3.648 A	2×470 uF
Multiphase Simulation	50 A	0.611 A	0.176 A		19.009 A	19.365 A	3.642 A

The 5-channel multiphase buck converter will have one-fifth the channel current of the conventional buck converter, resulting in an Rds(on) of 25 mΩ to meet the same efficiency requirement above. The on time of the buck FET will be the same, but the positive slope time of the current into the output capacitors will be based on the expressions below, along with its change in current.

Substituting Ton_out for Ton_ch and δI_out for δI_ch in the expression for the number of output capacitors results in two capacitors being required.

The input current will be the summation of the five, time-shifted, channel currents. The base frequency of the input current will be the number of channels times the channel frequency while its shape is a modified sawtooth waveform. Expressions for the duty cycle of the lower rise in current (DL) and the upper rise in current (DH) are presented. These two duty cycles and the two scalars (n3 and n4) are used to calculate the transition points of the input current waveform, as described in the following equations:

The input average current will be the same as the conventional buck. However, in this case, it's the product of the number of phases, the channel duty cycle and the average channel current. The expression for the input RMS current is the square root of the sum of the squares of the two trapezoidal currents that make up the input current waveform:

The capacitor RMS current then can be found using the expression for Ic_RMS above. The result of these equations was that the capacitor RMS current is 1.998 A, requiring two capacitors.

From the design example, it has been shown that the multiphase buck converter topology has reduced the required number of input capacitors from 14 to 2 and the output capacitors from 17 to 2. This has been accomplished by the reduction in ripple current seen by the input and output capacitors when the multiphase buck converter topology is employed (see the table.)

Two PSPICE models were developed to simulate the input current and the output current of the 5-channel multiphase converter to verify the calculated results. The results of the simulation agreed with the calculated results within less than a 1% error.

The increase in the output ripple frequency by the number of channels also will reduce the number of filtering capacitors at the load. Furthermore, the higher frequency will improve the response time to a load change. The control loop is allowed to have a greater bandwidth due to the higher output ripple frequency, resulting in faster transient response.

The multiphase buck converter topology also has more packaging advantages than just the reduction in the number of input and output capacitors. Each channel is converting power at a fraction of the conventional buck converter, which will reduce the size of the inductors and power MOSFETs used in the design. SMT inductors can be used along with SMT power MOSFETs (SOIC-8 package), resulting in a low-profile design. A multiphase buck converter designed to stepdown a 5-V input to 1.65-V output at 50 A has demonstrated a power-transfer efficiency of more than 80%, eliminating the need for heatsinks.

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