Research Battles Leakage in CMOS Chips

Jan 11, 2006 4:07 PM
By David Morrison, Editor, PETech

STMicroelectronics recently announced it has taken a leadership role in a new European Integrated Project called CLEAN, which stands for Controlling Leakage power in NanoCMOS SoCs. Co-funded by the European Commission, the three-year research project aims to develop solutions for controlling leakage currents in CMOS IC designs below 65 nm. These solutions will, in turn, extend battery life and reduce power consumption in electronic devices. The project will draw on the resources of a consortium of 14 European partners that includes representatives from industry and academia.

The importance of reducing leakage currents has grown tremendously with the development of integrated circuits manufactured using 65-nm and below features. Leakage currents are acknowledged by circuit designers to be the primary showstopper for future generations of ICs if the industry cannot find and adopt proper countermeasures.

To be successful, leakage-reducing countermeasures must be rooted in the design domain, as continuous process improvements are not expected to be sufficient to cope with the increased leakage currents in next-generation semiconductor devices. Therefore, this project is structured to develop a new generation of leakage power models, design methodologies and techniques, and prototype electronic design automation (EDA) tools. Together, these various models, methodologies and tools promise to manage and minimize leakage power even for very complex systems.

“The CLEAN project will help overcome the technological shortcomings on the 65-nm and below technology nodes, in particular leakage currents, process variability and unreliability,” said the project’s leader Roberto Zafalon, R&D program manager of Advanced System Technology, STMicroelectronics.

Within the CLEAN project, ST will manage and coordinate all of the activities of a consortium of 14 European partners consisting of semiconductor vendors, EDA vendors and academic and research institutes. In addition to ST, other members include Infineon Technologies AG, the Politecnico di Torino, ChipVision Design Systems AG, BullDAST, the Technical University of Denmark, theUniversitat Politecnica de Catalunya and the Commissariat à l’Energie Atomique LETI Laboratory. Others include the Politechnika Warszawska, Edacentrum GmbH, the Consorzio per la Ricerca e l’Educazione Permanente and the Budapest University of Technology and Economics.

Thanks to the competence mix of the project partners, encouraged by the European Commission, CLEAN’s results will provide great business opportunities for the advancements of the European nanoelectronics industry in different business sectors such as consumer electronics and EDA tools. For more information, see www.offis.de/projekte/projekt_e.php?id=176.

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